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Re: [3.4-BIB] Optimize cvtsd2ss for Athlon/K8
> On Wed, Nov 27, 2002 at 02:11:27PM +0100, Jan Hubicka wrote:
> > * i386.c (x86_sse_partial_regs_for_cvtsd2ss): New.
> > * i386.h (x86_sse_partial_regs_for_cvtsd2ss): Declare.
> > (TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS): New macro.
> > * i386.md (truncdfsf patterns and splitters): Use
> > TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
> Ok, except,
> > + /* Athlon optimizes partial-register FPS special case, thus avoiding the
> > + need for extra instructions beforehand */
> > + const int x86_sse_partial_regs_for_cvtsd2ss = 0;
> "0"? Surely you mean m_ATHLON_K8. Missing "." at end of comment.
No, x86_sse_partial_regs_for_cvtsd2ss does the same as
x86_sse_partial_regs does for all the other instructions.
For Athlon all the instructions needs reformating, with this single
Now the code to avoid reformating for cvtsd2ss is dead, but I didn't
find any other way I am happy about...
I guess if some other chip implements partial register types (Intel's
documentation is not clear enought to make me believe that P4 does or
don't do at the moment), it may or may not have this exception
implemented so I feel unconfortable with simply dropping the code here.