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Re: divmod with -O3
- From: Richard Henderson <rth at redhat dot com>
- To: Pierre Mallard <pierremallard at yahoo dot fr>
- Cc: gcc at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org
- Date: Tue, 19 Nov 2002 12:34:24 -0800
- Subject: Re: divmod with -O3
- References: <20021119162854.15137.qmail@web20305.mail.yahoo.com>
On Tue, Nov 19, 2002 at 05:28:54PM +0100, Pierre Mallard wrote:
> res = gen_reg_rtx(HImode);
> emit_insn (gen_rtx_PARALLEL(VOIDmode, gen_rtvec (2,
> gen_rtx_SET
> (VOIDmode,gen_rtx_SUBREG(QImode,res,0),gen_rtx_UDIV(QImode,operands[1],operands[2])),
> gen_rtx_SET
> (VOIDmode,gen_rtx_SUBREG(QImode,res,1),gen_rtx_UMOD(QImode,operands[1],operands[2]))
> )));
Your problem is going to be that you require two consecutive registers,
but did not express this so that rename_registers could honor it. Yes?
You're going to need to represent this some other way.
One option is to do
(define_insn_and_split ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(udiv:QI (match_operand:QI 3 "register_operand" "r")
(match_operand:QI 4 "register_operand" "r")))
(set (match_operand:QI 1 "nonimmediate_operand" "=rm")
(umod:QI (match_dup 3) (match_dup 4)))
(clobber (match_scratch:HI 2 "=r"))]
""
"#"
"reload_completed"
[(set (match_dup 2)
(unspec:HI [(match_dup 3) (match_dup 4)] UNSPEC_DIVMOD))
(set (match_dup 0) (match_dup 5))
(set (match_dup 1) (match_dup 6))]
{
operands[5] = gen_lowpart (QImode, operands[2]);
operands[6] = gen_highpart (QImode, operands[2]);
})
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(unspec:HI [(match_operand:QI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r")]
UNSPEC_DIVMOD))]
""
"...")
r~