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[patch] h8300.md: Add new patterns.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 15 Nov 2002 17:16:33 -0500 (EST)
- Subject: [patch] h8300.md: Add new patterns.
Hi,
Attached is a patch to add 4 new patterns.
When one needs to store things like "(a >> 8) & 0xff" into memory, gcc
produces awful code, emitting an actual shift followed by a QImode
store. Since H8 allows byte access to a register in SImode, we can
skip the shift.
Tested on h8300 port. Comitted.
Kazu Hirata
2002-11-15 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.md (4 anonymous patterns): New.
Index: h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.100
diff -u -r1.100 h8300.md
--- h8300.md 13 Nov 2002 01:11:58 -0000 1.100
+++ h8300.md 15 Nov 2002 22:05:05 -0000
@@ -2229,6 +2229,48 @@
[(set_attr "cc" "clobber")
(set_attr "length" "2")])
+;; Storing a part of HImode to QImode.
+
+(define_insn ""
+ [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
+ (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
+ (const_int 8)) 1))]
+ ""
+ "mov.b\\t%t1,%R0"
+ [(set_attr "cc" "set_znv")
+ (set_attr "length" "8")])
+
+;; Storing a part of SImode to QImode.
+
+(define_insn ""
+ [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
+ (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 8)) 3))]
+ ""
+ "mov.b\\t%x1,%R0"
+ [(set_attr "cc" "set_znv")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
+ (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 16)) 3))
+ (clobber (match_scratch:SI 2 "=&r"))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
+ [(set_attr "cc" "set_znv")
+ (set_attr "length" "8")])
+
+(define_insn ""
+ [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
+ (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 24)) 3))
+ (clobber (match_scratch:SI 2 "=&r"))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
+ [(set_attr "cc" "set_znv")
+ (set_attr "length" "8")])
+
(define_insn_and_split ""
[(set (pc)
(if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)