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Re: PowerPC PIC code addressibility tweak
- From: Segher Boessenkool <segher at koffie dot nl>
- To: David Edelsohn <dje at watson dot ibm dot com>, gcc-patches at gcc dot gnu dot org
- Date: Sun, 03 Nov 2002 04:06:36 +0100
- Subject: Re: PowerPC PIC code addressibility tweak
- References: <200211030239.VAA26112@makai.watson.ibm.com>
David Edelsohn wrote:
>
> >>>>> Segher Boessenkool writes:
>
> Segher> Another idea: why not generate something like
>
> Segher> bl $+4 ; blr
>
> Think about the instruction to which the blr instruction
> branches. Exercise for the reader.
David,
Oops. I feel so ashamed now :)
bl $+8 ; b $+8 ; blr
and
bl $+12 ; b $+12 ; .long XXXX ; blr
should work. I didn't do any timings though; as it's highly likely
that actual processors just look at the "31" in bcl 20,31,$+4 and not
at the "$+4" for the link-stack-or-not decision, my bets are your code
is better.
Segher