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[3.2-BIB] Canonicalize movss/movsd patterns
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, rth at cygnus dot com
- Date: Wed, 30 Oct 2002 23:36:33 +0100
- Subject: [3.2-BIB] Canonicalize movss/movsd patterns
Hi,
I would bet I've sent this patch already, but apparently I didn't.
It canonicalized movss and movsd patterns and fix one merging issue.
Wed Oct 30 23:33:53 CET 2002 Jan Hubicka <jh@suse.cz>
* i386.md (sse_loadss, sse_loadsd): Canonicalize; add expander
(movps, movpd splitters): Use canonical form.
(movv2di): Fix merge problem.
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.380.2.4
diff -c -3 -p -r1.380.2.4 i386.md
*** config/i386/i386.md 30 Oct 2002 22:09:18 -0000 1.380.2.4
--- config/i386/i386.md 30 Oct 2002 22:21:04 -0000
***************
*** 18254,18262 ****
"TARGET_SSE"
[(set (match_dup 0)
(vec_merge:V4SF
! (match_dup 1)
! (vec_duplicate:V4SF (float:SF (const_int 0)))
! (const_int 1)))])
(define_insn "movv4si_internal"
[(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
--- 18254,18266 ----
"TARGET_SSE"
[(set (match_dup 0)
(vec_merge:V4SF
! (vec_duplicate:V4SF (match_dup 1))
! (match_dup 2)
! (const_int 1)))]
! {
! operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
! operands[2] = CONST0_RTX (V4SFmode);
! })
(define_insn "movv4si_internal"
[(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
***************
*** 18289,18299 ****
(define_insn "movv2di_internal"
[(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,m")
(match_operand:V2DI 1 "nonimmediate_operand" "xm,x"))]
! "TARGET_SSE"
! ;; @@@ let's try to use movaps here.
! "movdqa\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_split
[(set (match_operand:V2DF 0 "register_operand" "")
--- 18293,18322 ----
(define_insn "movv2di_internal"
[(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,m")
(match_operand:V2DI 1 "nonimmediate_operand" "xm,x"))]
! "TARGET_SSE2"
! {
! if (get_attr_mode (insn) == MODE_V4SF)
! return "movaps\t{%1, %0|%0, %1}";
! else
! return "movdqa\t{%1, %0|%0, %1}";
! }
[(set_attr "type" "ssemov")
! (set (attr "mode")
! (cond [(eq_attr "alternative" "0")
! (if_then_else
! (ne (symbol_ref "optimize_size")
! (const_int 0))
! (const_string "V4SF")
! (const_string "TI"))
! (eq_attr "alternative" "1")
! (if_then_else
! (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
! (const_int 0))
! (ne (symbol_ref "optimize_size")
! (const_int 0)))
! (const_string "V4SF")
! (const_string "TI"))]
! (const_string "TI")))])
(define_split
[(set (match_operand:V2DF 0 "register_operand" "")
***************
*** 18301,18309 ****
"TARGET_SSE2"
[(set (match_dup 0)
(vec_merge:V2DF
! (match_dup 1)
! (vec_duplicate:V2DF (float:DF (const_int 0)))
! (const_int 1)))])
(define_insn "movv8qi_internal"
[(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
--- 18324,18336 ----
"TARGET_SSE2"
[(set (match_dup 0)
(vec_merge:V2DF
! (vec_duplicate:V2DF (match_dup 1))
! (match_dup 2)
! (const_int 1)))]
! {
! operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
! operands[2] = CONST0_RTX (V2DFmode);
! })
(define_insn "movv8qi_internal"
[(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
***************
*** 18875,18884 ****
(set_attr "mode" "V4SF")])
(define_insn "sse_loadss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF
! (match_operand:V4SF 1 "memory_operand" "m")
! (vec_duplicate:V4SF (float:SF (const_int 0)))
(const_int 1)))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
--- 18902,18920 ----
(set_attr "mode" "V4SF")])
(define_insn "sse_loadss"
+ [(match_operand:V4SF 0 "register_operand" "=x")
+ (match_operand:SF 1 "memory_operand" "m")]
+ "TARGET_SSE"
+ {
+ emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
+ CONST0_RTX (V4SFmode)));
+ })
+
+ (define_insn "sse_loadss_1"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(vec_merge:V4SF
! (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
! (match_operand:V4SF 2 "const0_operand" "X")
(const_int 1)))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
***************
*** 22287,22296 ****
(set_attr "mode" "V2DF")])
(define_insn "sse2_loadsd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_merge:V2DF
! (match_operand:DF 1 "memory_operand" "m")
! (vec_duplicate:DF (float:DF (const_int 0)))
(const_int 1)))]
"TARGET_SSE2"
"movsd\t{%1, %0|%0, %1}"
--- 22323,22341 ----
(set_attr "mode" "V2DF")])
(define_insn "sse2_loadsd"
+ [(match_operand:V2DF 0 "register_operand" "=x")
+ (match_operand:DF 1 "memory_operand" "m")]
+ "TARGET_SSE2"
+ {
+ emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
+ CONST0_RTX (V2DFmode)));
+ })
+
+ (define_insn "sse2_loadsd_1"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(vec_merge:V2DF
! (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
! (match_operand:V2DF 2 "const0_operand" "X")
(const_int 1)))]
"TARGET_SSE2"
"movsd\t{%1, %0|%0, %1}"