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Re: PowerPC register and memory cost update
- From: Dale Johannesen <dalej at apple dot com>
- To: Segher Boessenkool <segher at koffie dot nl>
- Cc: Dale Johannesen <dalej at apple dot com>, David Edelsohn <dje at watson dot ibm dot com>, gcc-patches at gcc dot gnu dot org
- Date: Thu, 24 Oct 2002 15:12:46 -0700
- Subject: Re: PowerPC register and memory cost update
On Thursday, October 24, 2002, at 01:42 PM, Segher Boessenkool wrote:
On a related note, looking at scheduling dumps (from -da), it seems to
me
that GCC thinks loads have latency of 2 cycles (correct) and
throughput of
1 per 2 cycles (incorrect for most cpu's, and certainly for the 7400 i
had
it optimize for: it can issue one load per cycle). This hurts my
indirect
threaded code interpreter a lot.
It knows that throughput is 1 cycle; the numbers are correct for 7400.
Could you point me at the "guilty" part of GCC? I just don't seem to
be
able to find where the issue rates are described.
In config/rs6000/rs6000.md; the "2 1" at the end are what you're
looking for.
Described in md.texi.
(define_function_unit "lsu" 1 0
(and (eq_attr "type" "load")
(eq_attr "cpu"
"rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
2 1)