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Re: Performance regression
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: Roger Sayle <roger at eyesopen dot com>, Dale Johannesen <dalej at apple dot com>
- Cc: Richard dot Earnshaw at arm dot com, Jim Wilson <wilson at redhat dot com>, gcc-patches at gcc dot gnu dot org
- Date: Wed, 25 Sep 2002 13:32:54 -0400
- Subject: Re: Performance regression
The PowerPC backend implements moves in common code in rs6000.c.
I think one would implement the equivalent to the ARM optimization with
the following patch. I am a little worried about selecting the correct
pseudo mode -- the load extend instruction is identical, but the resulting
mode may be wider than necessary.
David
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.385
diff -c -p -r1.385 rs6000.c
*** rs6000.c 20 Sep 2002 23:46:59 -0000 1.385
--- rs6000.c 25 Sep 2002 17:26:48 -0000
*************** rs6000_emit_move (dest, source, mode)
*** 2579,2586 ****
return;
}
! if (! no_new_pseudos && GET_CODE (operands[0]) != REG)
! operands[1] = force_reg (mode, operands[1]);
if (mode == SFmode && ! TARGET_POWERPC
&& TARGET_HARD_FLOAT && TARGET_FPRS
--- 2593,2612 ----
return;
}
! if (!no_new_pseudos)
! {
! if (GET_CODE (operands[1]) == MEM && optimize > 0)
! {
! rtx reg = gen_reg_rtx (Pmode);
!
! emit_insn (gen_rtx_SET (VOIDmode,
! reg,
! gen_rtx_ZERO_EXTEND (Pmode, operands[1])));
! operands[1] = gen_lowpart (mode, reg);
! }
! if (GET_CODE (operands[0]) != REG)
! operands[1] = force_reg (mode, operands[1]);
! }
if (mode == SFmode && ! TARGET_POWERPC
&& TARGET_HARD_FLOAT && TARGET_FPRS