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[Patch] sh64: anddi3 ICE

The attached patch fixes an sh64 ICE when compiling
vfscanf.c in glibc.  Sorry, I don't have a simple testcase.

Before register allocation we have the following RTL:

(insn:HI 17147 17146 17148 1343 (nil) (set (reg:SI 4960)
        (const_int 32768 [0x8000])) 125 {*movsi_media} (nil)
    (expr_list:REG_EQUIV (const_int 32768 [0x8000])
(insn:HI 13128 13126 13129 1370 0x40446600 (set (reg:DI 4961)
        (and:DI (subreg:DI (reg:SI 4959) 0)
            (subreg:DI (reg:SI 4960) 0))) 52 {anddi3} (insn_list 13126
    (expr_list:REG_DEAD (reg:SI 4959)
        (expr_list:REG_DEAD (reg:SI 4960)
            (expr_list:REG_EQUAL (and:DI (subreg:DI (reg:SI 4959) 0)
                    (const_int 32768 [0x8000]))

Regalloc fails to allocate a register to pseudo 4960.  Reload then
fixes up insn 13128 as:

(insn:HI 13128 13126 13129 1370 0x40446600 (set (reg:DI 1 r1 [4961])
        (and:DI (reg:DI 2 r2 [4959])
            (const_int 32768 [0x8000]))) 52 {anddi3} (insn_list 13126 (nil))
    (expr_list:REG_EQUAL (and:DI (subreg:DI (reg:SI 2 r2 [4959]) 0)
            (const_int 32768 [0x8000]))

(This satisfies the constraints for anddi3, although it does not
satisfy the third operand predicate.)  Subsequently, there is
a "cannot split insn" ICE, because this insn needs splitting, but
the split rule does not handle a constant with this value.

The patch tightens up the constraint so that it only allows the
constants that the split is willing to handle.  An alternative
fix would be to accept any constant operand and split appropriately.
I wasn't sure which was the best way to go ... this patch is closer
to the behaviour before the mshfl tweaks were added.

Regression tested on sh64-unknown-elf/sh64-sim.


Attachment: anddi3-patch.txt
Description: anddi3-patch.txt

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