This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Fix failure of execute/built-in-setjmp.c on hppa64-hp-hpux11*

This fixes a problem noted where the frame pointer restoration and the
pic register restoration after a longjmp got interchanged in scheduling.
I believe this is because the dependence of the pic register restore
on the frame pointer is not clear at the point in the rtl where this
interchange occurs.  We just have the pic register being saved and
restored from a pseudo register.

Applied to main.

J. David Anglin                        
National Research Council of Canada              (613) 990-0752 (FAX: 952-6605)

2002-09-09  John David Anglin  <>

	* (exception_receiver, builtin_setjmp_receiver): Add blockage
	on TARGET_64BIT before pic register restore.

Index: config/pa/
RCS file: /cvsroot/gcc/gcc/gcc/config/pa/,v
retrieving revision 1.111
diff -u -3 -p -r1.111
--- config/pa/	4 Sep 2002 22:05:43 -0000	1.111
+++ config/pa/	9 Sep 2002 21:03:05 -0000
@@ -7455,6 +7455,12 @@
+  /* On the 64-bit port, we need a blockage because there is
+     confusion regarding the dependence of the restore on the
+     frame pointer.  As a result, the frame pointer and pic
+     register restores sometimes are interchanged erroneously.  */
+  if (TARGET_64BIT)
+    emit_insn (gen_blockage ());
   /* Restore the PIC register using hppa_pic_save_rtx ().  The
      PIC register is not saved in the frame in 64-bit ABI.  */
   emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
@@ -7466,6 +7472,8 @@
+  if (TARGET_64BIT)
+    emit_insn (gen_blockage ());
   /* Restore the PIC register.  Hopefully, this will always be from
      a stack slot.  The only registers that are valid after a
      builtin_longjmp are the stack and frame pointers.  */

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]