Re: restore performance for -fnew-ra

[Michael Matz <matz at suse dot de>]

Hi,

On Thu, 29 Aug 2002, Richard Henderson wrote:

> > That's why I didn't bother documenting that
> > define in the texinfo, and also why I didn't add it to defaults.h.  Should
> > I nevertheless?
>
> Yes.

Ok, then it's here again (bootstraps without regression on x86 linux):


Ciao,
Michael.
-- 
        * i386/i386.h (SPILL_REGS): Define.
        * defaults.h (SPILL_REGS): Define, if not yet defined.
        * ra-build.c (remember_web_was_spilled): Use it.
        * doc/tm.texi: Document it.

Index: ra-build.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/ra-build.c,v
retrieving revision 1.7
diff -u -p -r1.7 ra-build.c
--- ra-build.c	14 Aug 2002 03:09:14 -0000	1.7
+++ ra-build.c	2 Sep 2002 08:39:51 -0000
@@ -121,7 +121,6 @@ static void init_bb_info PARAMS ((void))
 static void free_bb_info PARAMS ((void));
 static void build_web_parts_and_conflicts PARAMS ((struct df *));

-
 /* A sbitmap of DF_REF_IDs of uses, which are live over an abnormal
    edge.  */
 static sbitmap live_over_abnormal;
@@ -2358,7 +2357,7 @@ remember_web_was_spilled (web)
     }
   else
     COPY_HARD_REG_SET (web->usable_regs,
-		       reg_class_contents[(int) GENERAL_REGS]);
+		       reg_class_contents[(int) SPILL_REGS]);
   AND_COMPL_HARD_REG_SET (web->usable_regs, never_use_colors);
   prune_hardregs_for_mode (&web->usable_regs, PSEUDO_REGNO_MODE (web->regno));
 #ifdef CLASS_CANNOT_CHANGE_MODE
Index: defaults.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/defaults.h,v
retrieving revision 1.89
diff -u -p -r1.89 defaults.h
--- defaults.h	21 Aug 2002 02:41:43 -0000	1.89
+++ defaults.h	2 Sep 2002 08:39:51 -0000
@@ -589,4 +589,11 @@ You Lose!  You must define PREFERRED_DEB
 #define EXTRA_ADDRESS_CONSTRAINT(C) 0
 #endif

+/* SPILL_REGS is a reg class of those registers which can possibly
+   be used to load values for spilled webs (i.e. registers which are
+   allocated to the small webs into which a spilled web is split).  */
+#ifndef SPILL_REGS
+#define SPILL_REGS ALL_REGS
+#endif
+
 #endif  /* ! GCC_DEFAULTS_H */
Index: doc/tm.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/tm.texi,v
retrieving revision 1.160
diff -u -p -r1.160 tm.texi
--- doc/tm.texi	30 Aug 2002 19:18:51 -0000	1.160
+++ doc/tm.texi	2 Sep 2002 08:39:51 -0000
@@ -2343,6 +2343,15 @@ may serve in each capacity.  The compile
 looking for one that is valid, and will reload one or both registers
 only if neither labeling works.

+@findex SPILL_REGS
+@item SPILL_REGS
+A macro specifying a certain register class which is used to hold
+spilled values.  Most machines won't define this, in which case it defaults
+to ALL_REGS, but some architectures can't use certain registers in a
+function without special preparation although HARD_REGNO_MODE_OK says so
+(e.g. MMX_REGS on x86).  Those should be excluded from this class.  Other
+than that it should be the broadest possible class.
+
 @findex PREFERRED_RELOAD_CLASS
 @item PREFERRED_RELOAD_CLASS (@var{x}, @var{class})
 A C expression that places additional restrictions on the register class
Index: config/i386/i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.280
diff -u -p -r1.280 i386.h
--- config/i386/i386.h	31 Jul 2002 23:18:43 -0000	1.280
+++ config/i386/i386.h	2 Sep 2002 08:39:51 -0000
@@ -1178,6 +1178,7 @@ enum reg_class
 };

 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
+#define SPILL_REGS FLOAT_INT_SSE_REGS

 #define INTEGER_CLASS_P(CLASS) \
   reg_class_subset_p ((CLASS), GENERAL_REGS)