[PATCH' RFA] mips "Branch Likely" handling behaviour, options.

[cgd at broadcom dot com]

Following the discussion of the previous version of the patch & the
suggestions that came up, I've converted the patch to use a target
flag.

builds & checks for mipsisa32-elf (from host x86-linux), w/ no
regressions.  I verified by hand that the flags have the expected
effects.


the only interesting part about this is that I don't any longer check
for MIPS16 in ISA_HAS_BRANCHLIKELY.  TARGET_MIPS16 is checked in
GENERATE_BRANCHLIKELY, so branch likely insns won't be generated if
creating MIPS16 code.  No worries there.

The notion behind that change goes as follows:

One might start with a base set of flags like:

	-march=mips64 -mbranch-likely

to which one might want to add, when compiling a few modules, -mips16.
If one did have -march=mips64 -mbranch-likely -mips16, and one did
check for MIPS16 in ISA_HAS_BRANCHLIKELY, the code would generate a
spurious warning.  MIPS16 really layers on to a 'base' architecture,
and the base architecture may well have branch likely
instructions... but regardless of whether it does, and regardless of
the setting of TARGET_BRANCHLIKELY, they will never be used for MIPS16
since MIPS16 doesn't have them.


cgd
===================================================================
2002-08-02  Chris Demetriou  <cgd@broadcom.com>

	* config/mips/mips.c (override_options): Set MASK_BRANCHLIKELY
	in target_flags based on ISA, if it was not set on the command
	line.  Warn if MASK_BRANCHLIKLEY is set but the ISA does not
	support Branch Likely instructions.
	* config/mips/mips.h (MASK_BRANCHLIKLEY): New macro.
	(TARGET_BRANCHLIKELY): Likewise.
	(TARGET_SWITCHES): Add -mbranch-likely and -mno-branch-likely.
	(GENERATE_BRANCHLIKELY): Use TARGET_BRANCHLIKELY rather than
	ISA_HAS_BRANCHLIKELY.
	(ISA_HAS_BRANCHLIKELY): Do not include MIPS16 check.
	* doc/invoke.texi: Document new MIPS -mbranch-likely and
	-mno-branch-likely options.
	
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.222
diff -u -p -r1.222 mips.c
--- config/mips/mips.c	2 Aug 2002 14:55:08 -0000	1.222
+++ config/mips/mips.c	3 Aug 2002 06:34:53 -0000
@@ -5177,6 +5177,31 @@ override_options ()
   if (mips_abi != ABI_32 && mips_abi != ABI_O64)
     flag_pcc_struct_return = 0;
 
+  if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
+    {
+      /* If neither -mbranch-likely nor -mno-branch-likely was given
+	 on the command line, set MASK_BRANCHLIKELY based on the target
+	 architecture.
+
+	 By default, we enable use of Branch Likely instructions on
+	 all architectures which support them except for MIPS32 and MIPS64
+	 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
+	 implement them).
+
+	 The MIPS32 and MIPS64 architecture specifications say "Software
+	 is strongly encouraged to avoid use of Branch Likely
+	 instructions, as they will be removed from a future revision
+	 of the [MIPS32 and MIPS64] architecture."  Therefore, we do not
+	 issue those instructions unless instructed to do so by
+	 -mbranch-likely.  */
+      if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS64))
+	target_flags |= MASK_BRANCHLIKELY;
+      else
+	target_flags &= ~MASK_BRANCHLIKELY;
+    }
+  if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
+    warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
+
   /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined.  We need
      to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work.  */
   /* ??? -non_shared turns off pic code generation, but this is not
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.210
diff -u -p -r1.210 mips.h
--- config/mips/mips.h	2 Aug 2002 20:22:35 -0000	1.210
+++ config/mips/mips.h	3 Aug 2002 06:34:53 -0000
@@ -232,6 +232,8 @@ extern void		sbss_section PARAMS ((void)
 					   consts in rodata */
 #define MASK_NO_FUSED_MADD 0x01000000   /* Don't generate floating point
 					   multiply-add operations.  */
+#define MASK_BRANCHLIKELY  0x02000000   /* Generate Branch Likely
+					   instructions.  */
 
 					/* Debug switches, not documented */
 #define MASK_DEBUG	0		/* unused */
@@ -322,6 +324,8 @@ extern void		sbss_section PARAMS ((void)
 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
 #define TARGET_CHECK_RANGE_DIV  (target_flags & MASK_CHECK_RANGE_DIV)
 
+#define TARGET_BRANCHLIKELY	(target_flags & MASK_BRANCHLIKELY)
+
 /* This is true if we must enable the assembly language file switching
    code.  */
 
@@ -608,6 +612,10 @@ extern void		sbss_section PARAMS ((void)
      N_("Trap on integer divide overflow")},				\
   {"no-check-range-division",-MASK_CHECK_RANGE_DIV,			\
      N_("Don't trap on integer divide overflow")},			\
+  { "branch-likely",      MASK_BRANCHLIKELY,				\
+      N_("Use Branch Likely instructions, overriding default for arch")}, \
+  { "no-branch-likely",  -MASK_BRANCHLIKELY,				\
+      N_("Don't use Branch Likely instructions, overriding default for arch")}, \
   {"debug",		  MASK_DEBUG,					\
      NULL},								\
   {"debuga",		  MASK_DEBUG_A,					\
@@ -741,7 +749,7 @@ extern void		sbss_section PARAMS ((void)
 /* This is meant to be redefined in the host dependent files.  */
 #define SUBTARGET_TARGET_OPTIONS
 
-#define GENERATE_BRANCHLIKELY   (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
+#define GENERATE_BRANCHLIKELY   (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
 
 /* Generate three-operand multiply instructions for SImode.  */
 #define GENERATE_MULT3_SI       ((TARGET_MIPS3900                       \
@@ -776,8 +784,7 @@ extern void		sbss_section PARAMS ((void)
 /* ISA has branch likely instructions (eg. mips2).  */
 /* Disable branchlikely for tx39 until compare rewrite.  They haven't
    been generated up to this point.  */
-#define ISA_HAS_BRANCHLIKELY	(!ISA_MIPS1				\
-				 && !TARGET_MIPS16)
+#define ISA_HAS_BRANCHLIKELY	(!ISA_MIPS1)
 
 /* ISA has the conditional move instructions introduced in mips4.  */
 #define ISA_HAS_CONDMOVE        ((ISA_MIPS4				\
Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.165
diff -u -p -r1.165 invoke.texi
--- doc/invoke.texi	2 Aug 2002 01:16:09 -0000	1.165
+++ doc/invoke.texi	3 Aug 2002 06:34:54 -0000
@@ -477,7 +477,8 @@ in the following sections.
 -m4650  -msingle-float  -mmad @gol
 -mstats  -EL  -EB  -G @var{num}  -nocpp @gol
 -mabi=32  -mabi=n32  -mabi=64  -mabi=eabi @gol
--mfix7000  -mno-crt0 -mflush-func=@var{func} -mno-flush-func}
+-mfix7000  -mno-crt0 -mflush-func=@var{func} -mno-flush-func
+-mbranch-likely -mno-branch-likely}
 
 @emph{i386 and x86-64 Options}
 @gccoptlist{
@@ -7360,6 +7361,18 @@ memory range for which the cache is bein
 memory range, and the number 3 (to flush both caches).  The default
 depends on the target gcc was configured for, but commonly is either
 @samp{_flush_func} or @samp{__cpu_flush}.
+
+@item -mbranch-likely
+@itemx -mno-branch-likely
+@opindex mbranch-likely
+@opindex mno-branch-likely
+Enable or disable use of Branch Likely instructions, regardless of the
+default for the selected architecture.  By default, Branch Likely
+instructions may be generated if they are supported by the selected
+architecture.  An exception is for the MIPS32 and MIPS64 architectures
+and processors which implement those architectures; for those, Branch
+Likely instructions will not be generated by default because the MIPS32
+and MIPS64 architectures specifically deprecate their use.
 @end table
 
 These options are defined by the macro