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Fix for sgtu conditions in mips.md
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 01 Aug 2002 20:24:57 +0100
- Subject: Fix for sgtu conditions in mips.md
There are mips16 and non-mips16 versions of the sgtu patterns, but the
TARGET_MIPS16 conditions seem to have got lost somewhere. As far as I
can tell, we don't actually generate the mips16 sgtu directly, but
combine can create one for:
int f (unsigned long long x, int y) { return x < y; }
since it creates:
(ltu (reg R1)
(sign_extend (reg R2)))
by combining instructions and thinks it's more canonical to
have sign_extend as the first operand:
(gtu (sign_extend (reg R2))
(reg R1))
Tested on mips-elf & mips-sgi-irix6.5, no regressions. Fixes the
above test case for mips16. OK to install?
Richard
* config/mips/mips.md: Add [!]TARGET_MIPS16 to sgtu conditions.
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.138
diff -u -d -p -r1.138 mips.md
--- config/mips/mips.md 31 Jul 2002 08:53:55 -0000 1.138
+++ config/mips/mips.md 1 Aug 2002 09:37:31 -0000
@@ -8823,7 +8823,7 @@ move\\t%0,%z4\\n\\
[(set (match_operand:SI 0 "register_operand" "=d")
(gtu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "reg_or_0_operand" "dJ")))]
- ""
+ "!TARGET_MIPS16"
"sltu\\t%0,%z2,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -8832,7 +8832,7 @@ move\\t%0,%z4\\n\\
[(set (match_operand:SI 0 "register_operand" "=t")
(gtu:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))]
- ""
+ "TARGET_MIPS16"
"sltu\\t%2,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -8841,7 +8841,7 @@ move\\t%0,%z4\\n\\
[(set (match_operand:DI 0 "register_operand" "=d")
(gtu:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
- "TARGET_64BIT"
+ "TARGET_64BIT && !TARGET_MIPS16"
"sltu\\t%0,%z2,%1"
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
@@ -8850,7 +8850,7 @@ move\\t%0,%z4\\n\\
[(set (match_operand:DI 0 "register_operand" "=t")
(gtu:DI (match_operand:DI 1 "se_register_operand" "d")
(match_operand:DI 2 "se_register_operand" "d")))]
- "TARGET_64BIT"
+ "TARGET_64BIT && TARGET_MIPS16"
"sltu\\t%2,%1"
[(set_attr "type" "arith")
(set_attr "mode" "DI")])