Index: config/sh/little.h
===================================================================
RCS file: config/sh/little.h
diff -N config/sh/little.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ config/sh/little.h	17 May 2002 21:08:48 -0000
@@ -0,0 +1,22 @@
+/* Definition of little endian SH machine for GNU compiler.
+
+   Copyright (C) 2002 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define TARGET_ENDIAN_DEFAULT LITTLE_ENDIAN_BIT
Index: config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.142
diff -u -r1.142 sh.h
--- config/sh/sh.h	15 May 2002 05:29:59 -0000	1.142
+++ config/sh/sh.h	17 May 2002 21:08:52 -0000
@@ -24,9 +24,40 @@
 #ifndef GCC_SH_H
 #define GCC_SH_H
 
+/* This defaults us to big-endian.  */
+#ifndef TARGET_ENDIAN_DEFAULT
+#define TARGET_ENDIAN_DEFAULT 0
+#endif 
+
 #define TARGET_VERSION \
   fputs (" (Hitachi SH)", stderr);
 
+/* Run-time compilation parameters selecting different hardware subsets.
+   Define these early; we need them later on.  */
+
+extern int target_flags;
+#define ISIZE_BIT      	(1<<1)
+#define DALIGN_BIT     	(1<<6)
+#define SH1_BIT	       	(1<<8)
+#define SH2_BIT	       	(1<<9)
+#define SH3_BIT	       	(1<<10)
+#define SH3E_BIT	(1<<11)
+#define HARD_SH4_BIT	(1<<5)
+#define FPU_SINGLE_BIT	(1<<7)
+#define SH4_BIT	       	(1<<12)
+#define FMOVD_BIT	(1<<4)
+#define SH5_BIT		(1<<0)
+#define SPACE_BIT 	(1<<13)
+#define BIGTABLE_BIT  	(1<<14)
+#define RELAX_BIT	(1<<15)
+#define USERMODE_BIT	(1<<16)
+#define HITACHI_BIT     (1<<22)
+#define NOMACSAVE_BIT   (1<<23)
+#define PREFERGOT_BIT	(1<<24)
+#define PADSTRUCT_BIT  (1<<28)
+#define LITTLE_ENDIAN_BIT (1<<29)
+#define IEEE_BIT (1<<30)
+
 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h.  We can't
    include it here, because hconfig.h is also included by gencodes.c .  */
 /* ??? No longer true.  */
@@ -62,7 +93,13 @@
 %(subtarget_cpp_endian_spec) "
 
 #ifndef SUBTARGET_CPP_ENDIAN_SPEC
-#define SUBTARGET_CPP_ENDIAN_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
+#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#define SUBTARGET_CPP_ENDIAN_SPEC \
+  "%{mb:-D__BIG_ENDIAN__} %{!mb:-D__LITTLE_ENDIAN__}"
+#else
+#define SUBTARGET_CPP_ENDIAN_SPEC \
+  "%{ml:-D__LITTLE_ENDIAN__} %{!ml:-D__BIG_ENDIAN__}"
+#endif
 #endif
 
 #ifndef SUBTARGET_CPP_SPEC
@@ -85,7 +122,11 @@
 #define ASM_SPEC  "%(subtarget_asm_endian_spec) %{mrelax:-relax}"
 
 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
-#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little}"
+#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
+#else
+#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
+#endif
 #endif
 
 #define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
@@ -132,31 +173,6 @@
 /* ??? Need to write documentation for all SH options and add it to the
    invoke.texi file.  */
 
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-extern int target_flags;
-#define ISIZE_BIT      	(1<<1)
-#define DALIGN_BIT     	(1<<6)
-#define SH1_BIT	       	(1<<8)
-#define SH2_BIT	       	(1<<9)
-#define SH3_BIT	       	(1<<10)
-#define SH3E_BIT	(1<<11)
-#define HARD_SH4_BIT	(1<<5)
-#define FPU_SINGLE_BIT	(1<<7)
-#define SH4_BIT	       	(1<<12)
-#define FMOVD_BIT	(1<<4)
-#define SH5_BIT		(1<<0)
-#define SPACE_BIT 	(1<<13)
-#define BIGTABLE_BIT  	(1<<14)
-#define RELAX_BIT	(1<<15)
-#define USERMODE_BIT	(1<<16)
-#define HITACHI_BIT     (1<<22)
-#define NOMACSAVE_BIT   (1<<23)
-#define PREFERGOT_BIT	(1<<24)
-#define PADSTRUCT_BIT  (1<<28)
-#define LITTLE_ENDIAN_BIT (1<<29)
-#define IEEE_BIT (1<<30)
-
 /* Nonzero if we should dump out instruction size info.  */
 #define TARGET_DUMPISIZE  (target_flags & ISIZE_BIT)
 
@@ -315,7 +331,7 @@
 /* This are meant to be redefined in the host dependent files */
 #define SUBTARGET_SWITCHES
 
-#define TARGET_DEFAULT  (SH1_BIT)
+#define TARGET_DEFAULT  (SH1_BIT|TARGET_ENDIAN_DEFAULT)
 
 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE)				\
 do {									\
Index: config/sh/sh64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh64.h,v
retrieving revision 1.4
diff -u -r1.4 sh64.h
--- config/sh/sh64.h	15 May 2002 05:29:59 -0000	1.4
+++ config/sh/sh64.h	17 May 2002 21:08:52 -0000
@@ -46,7 +46,7 @@
 %{mrelax:-relax}"
 
 #undef TARGET_DEFAULT
-#define TARGET_DEFAULT  (SH5_BIT|SH4_BIT|SH3E_BIT)
+#define TARGET_DEFAULT  (SH5_BIT|SH4_BIT|SH3E_BIT|TARGET_ENDIAN_DEFAULT)
 
 #undef SH_ELF_WCHAR_TYPE
 #define SH_ELF_WCHAR_TYPE "int"
Index: config/sh/t-be
===================================================================
RCS file: config/sh/t-be
diff -N config/sh/t-be
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ config/sh/t-be	17 May 2002 21:08:52 -0000
@@ -0,0 +1 @@
+MULTILIB_OPTIONS= ml
Index: config/sh/t-le
===================================================================
RCS file: config/sh/t-le
diff -N config/sh/t-le
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ config/sh/t-le	17 May 2002 21:08:52 -0000
@@ -0,0 +1 @@
+MULTILIB_OPTIONS= mb