This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
altivec: add vscr register
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: dje at watson dot ibm dot com, gcc-patches at gcc dot gnu dot org
- Date: Wed, 15 May 2002 16:41:11 +1000
- Subject: altivec: add vscr register
hello.
consider this:
foo()
{
vector int result;
result = vec_adds(blah, blah);
__check_for_saturation__
}
gcc, will optimize away vec_adds() because the result is a local
variable unused later. then when we check the saturation bit in VSCR,
we get wrong results.
this patch explains to gcc all about VSCR, and adds it as a global
register as well.
with this patch and my upcoming reload patch, motorola's entire
altivec testsuite passes. sigh, about time.
ok for mainline?
2002-05-15 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md ("altivec_mtvscr"): Set VSCR register.
("altivec_mfvscr"): Read from VSCR.
Add vscr sets for the following insns: altivec_vctuxs,
altivec_vaddubs, altivec_vaddsbs, altivec_vadduhs,
altivec_vaddshs, altivec_vadduws, altivec_vaddsws, altivec_vctsxs,
altivec_vmhaddshs, altivec_vmhraddshs, altivec_vmsumuhs,
altivec_vmsumshs, altivec_vpkuhss, altivec_vpkshss,
altivec_vpkuwss, altivec_vpkswss, altivec_vpkuhus,
altivec_vpkshus, altivec_vpkuwus, altivec_vpkswus,
altivec_vsububs, altivec_vsubsbs, altivec_vsubuhs,
altivec_vsubshs, altivec_vsubuws, altivec_vsubsws,
altivec_vsum4ubs, altivec_vsum4sbs, altivec_vsum4shs,
altivec_vsum2sws, altivec_vsumsws.
* config/rs6000/rs6000.h: Add VSCR fixed register.
(CALL_REALLY_USED_REGISTERS): Add vscr.
(CALL_USED_REGISTERS): Same.
(FIXED_REGISTERS): Same.
(REG_ALLOC_ORDER): Same.
(reg_class): Add VSCR_REGS.
(REG_CLASS_NAMES): Same.
(REG_CLASS_CONTENTS): Same.
(VSCR_REGNO): New.
(REGISTER_NAMES): Add vscr.
(DEBUG_REGISTER_NAMES): Same.
(ADDITIONAL_REGISTER_NAMES): Same.
(FIRST_PSEUDO_REGISTER): Increment.
(CONDITIONAL_REGISTER_USAGE): Set VSCR as a global register.
* reload1.c (forget_old_reloads_1): Do not use subreg offset.
Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.200
diff -c -p -r1.200 rs6000.h
*** config/rs6000/rs6000.h 1 May 2002 01:50:24 -0000 1.200
--- config/rs6000/rs6000.h 15 May 2002 06:34:40 -0000
*************** extern int rs6000_altivec_vrsave;
*** 673,679 ****
a register, in order to work around problems in allocating stack storage
in inline functions. */
! #define FIRST_PSEUDO_REGISTER 110
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
--- 673,679 ----
a register, in order to work around problems in allocating stack storage
in inline functions. */
! #define FIRST_PSEUDO_REGISTER 111
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
*************** extern int rs6000_altivec_vrsave;
*** 697,703 ****
/* AltiVec registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
! 1 \
}
/* 1 for registers not available across function calls.
--- 697,703 ----
/* AltiVec registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
! 1, 1 \
}
/* 1 for registers not available across function calls.
*************** extern int rs6000_altivec_vrsave;
*** 716,722 ****
/* AltiVec registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
! 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
--- 716,722 ----
/* AltiVec registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
! 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
*************** extern int rs6000_altivec_vrsave;
*** 734,740 ****
/* AltiVec registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
! 0 \
}
#define MQ_REGNO 64
--- 734,740 ----
/* AltiVec registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
! 0, 0 \
}
#define MQ_REGNO 64
*************** extern int rs6000_altivec_vrsave;
*** 749,754 ****
--- 749,755 ----
#define LAST_ALTIVEC_REGNO 108
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
#define VRSAVE_REGNO 109
+ #define VSCR_REGNO 110
/* List the order in which to allocate registers. Each register must be
listed once, even those in FIXED_REGISTERS.
*************** extern int rs6000_altivec_vrsave;
*** 771,777 ****
mq (not saved; best to use it if we can)
ctr (not saved; when we have the choice ctr is better)
lr (saved)
! cr5, r1, r2, ap, xer, vrsave (fixed)
AltiVec registers:
v0 - v1 (not saved or used for anything)
--- 772,778 ----
mq (not saved; best to use it if we can)
ctr (not saved; when we have the choice ctr is better)
lr (saved)
! cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
AltiVec registers:
v0 - v1 (not saved or used for anything)
*************** extern int rs6000_altivec_vrsave;
*** 802,808 ****
79, \
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
! 97, 109 \
}
/* True if register is floating-point. */
--- 803,809 ----
79, \
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
! 97, 109, 110 \
}
/* True if register is floating-point. */
*************** extern int rs6000_altivec_vrsave;
*** 957,962 ****
--- 958,965 ----
= fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
= call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
= call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
+ if (TARGET_ALTIVEC) \
+ global_regs[VSCR_REGNO] = 1; \
if (! TARGET_ALTIVEC) \
{ \
for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
*************** enum reg_class
*** 1041,1046 ****
--- 1044,1050 ----
FLOAT_REGS,
ALTIVEC_REGS,
VRSAVE_REGS,
+ VSCR_REGS,
NON_SPECIAL_REGS,
MQ_REGS,
LINK_REGS,
*************** enum reg_class
*** 1068,1073 ****
--- 1072,1078 ----
"FLOAT_REGS", \
"ALTIVEC_REGS", \
"VRSAVE_REGS", \
+ "VSCR_REGS", \
"NON_SPECIAL_REGS", \
"MQ_REGS", \
"LINK_REGS", \
*************** enum reg_class
*** 1094,1099 ****
--- 1099,1105 ----
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
{ 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
{ 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
*************** enum reg_class
*** 1126,1131 ****
--- 1132,1138 ----
: (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
: (REGNO) == XER_REGNO ? XER_REGS \
: (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
+ : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
: NO_REGS)
/* The class value for index registers, and the one for base regs. */
*************** extern char rs6000_reg_names[][8]; /* re
*** 2616,2621 ****
--- 2623,2629 ----
&rs6000_reg_names[107][0], /* v30 */ \
&rs6000_reg_names[108][0], /* v31 */ \
&rs6000_reg_names[109][0], /* vrsave */ \
+ &rs6000_reg_names[110][0], /* vscr */ \
}
/* print-rtl can't handle the above REGISTER_NAMES, so define the
*************** extern char rs6000_reg_names[][8]; /* re
*** 2639,2645 ****
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
! "vrsave" \
}
/* Table of additional register names to use in user input. */
--- 2647,2653 ----
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
! "vrsave", "vscr" \
}
/* Table of additional register names to use in user input. */
*************** extern char rs6000_reg_names[][8]; /* re
*** 2669,2675 ****
{"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
{"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
{"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
! {"vrsave", 109}, \
/* no additional names for: mq, lr, ctr, ap */ \
{"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
{"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
--- 2677,2683 ----
{"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
{"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
{"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
! {"vrsave", 109}, {"vscr", 110}, \
/* no additional names for: mq, lr, ctr, ap */ \
{"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
{"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.185
diff -c -p -r1.185 rs6000.md
*** config/rs6000/rs6000.md 7 May 2002 02:48:06 -0000 1.185
--- config/rs6000/rs6000.md 15 May 2002 06:34:43 -0000
***************
*** 14145,14151 ****
(define_insn "altivec_vaddubs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 36))]
"TARGET_ALTIVEC"
"vaddubs %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 14145,14152 ----
(define_insn "altivec_vaddubs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 36))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vaddubs %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 14153,14159 ****
(define_insn "altivec_vaddsbs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 37))]
"TARGET_ALTIVEC"
"vaddsbs %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 14154,14161 ----
(define_insn "altivec_vaddsbs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 37))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vaddsbs %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 14161,14167 ****
(define_insn "altivec_vadduhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 38))]
"TARGET_ALTIVEC"
"vadduhs %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 14163,14170 ----
(define_insn "altivec_vadduhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 38))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vadduhs %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 14169,14175 ****
(define_insn "altivec_vaddshs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 39))]
"TARGET_ALTIVEC"
"vaddshs %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 14172,14179 ----
(define_insn "altivec_vaddshs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 39))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vaddshs %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 14177,14183 ****
(define_insn "altivec_vadduws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 40))]
"TARGET_ALTIVEC"
"vadduws %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 14181,14188 ----
(define_insn "altivec_vadduws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 40))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vadduws %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 14185,14191 ****
(define_insn "altivec_vaddsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 41))]
"TARGET_ALTIVEC"
"vaddsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 14190,14197 ----
(define_insn "altivec_vaddsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 41))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vaddsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 14432,14438 ****
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V4SI 3 "register_operand" "v")] 69))]
"TARGET_ALTIVEC"
"vmsumuhs %0, %1, %2, %3"
[(set_attr "type" "veccomplex")])
--- 14438,14445 ----
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V4SI 3 "register_operand" "v")] 69))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vmsumuhs %0, %1, %2, %3"
[(set_attr "type" "veccomplex")])
***************
*** 14441,14447 ****
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V4SI 3 "register_operand" "v")] 70))]
"TARGET_ALTIVEC"
"vmsumshs %0, %1, %2, %3"
[(set_attr "type" "veccomplex")])
--- 14448,14455 ----
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V4SI 3 "register_operand" "v")] 70))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vmsumshs %0, %1, %2, %3"
[(set_attr "type" "veccomplex")])
***************
*** 14506,14512 ****
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V8HI 3 "register_operand" "v")] 71))]
"TARGET_ALTIVEC"
"vmhaddshs %0, %1, %2, %3"
[(set_attr "type" "veccomplex")])
--- 14514,14521 ----
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V8HI 3 "register_operand" "v")] 71))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vmhaddshs %0, %1, %2, %3"
[(set_attr "type" "veccomplex")])
***************
*** 14514,14520 ****
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V8HI 3 "register_operand" "v")] 72))]
"TARGET_ALTIVEC"
"vmhraddshs %0, %1, %2, %3"
[(set_attr "type" "veccomplex")])
--- 14523,14530 ----
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V8HI 3 "register_operand" "v")] 72))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vmhraddshs %0, %1, %2, %3"
[(set_attr "type" "veccomplex")])
***************
*** 14801,14807 ****
(define_insn "altivec_vpkuhss"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 96))]
"TARGET_ALTIVEC"
"vpkuhss %0,%1,%2"
[(set_attr "type" "vecperm")])
--- 14811,14818 ----
(define_insn "altivec_vpkuhss"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 96))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vpkuhss %0,%1,%2"
[(set_attr "type" "vecperm")])
***************
*** 14809,14815 ****
(define_insn "altivec_vpkshss"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 97))]
"TARGET_ALTIVEC"
"vpkshss %0,%1,%2"
[(set_attr "type" "vecperm")])
--- 14820,14827 ----
(define_insn "altivec_vpkshss"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 97))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vpkshss %0,%1,%2"
[(set_attr "type" "vecperm")])
***************
*** 14817,14823 ****
(define_insn "altivec_vpkuwss"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 98))]
"TARGET_ALTIVEC"
"vpkuwss %0,%1,%2"
[(set_attr "type" "vecperm")])
--- 14829,14836 ----
(define_insn "altivec_vpkuwss"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 98))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vpkuwss %0,%1,%2"
[(set_attr "type" "vecperm")])
***************
*** 14825,14831 ****
(define_insn "altivec_vpkswss"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 99))]
"TARGET_ALTIVEC"
"vpkswss %0,%1,%2"
[(set_attr "type" "vecperm")])
--- 14838,14845 ----
(define_insn "altivec_vpkswss"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 99))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vpkswss %0,%1,%2"
[(set_attr "type" "vecperm")])
***************
*** 14833,14839 ****
(define_insn "altivec_vpkuhus"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 100))]
"TARGET_ALTIVEC"
"vpkuhus %0,%1,%2"
[(set_attr "type" "vecperm")])
--- 14847,14854 ----
(define_insn "altivec_vpkuhus"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 100))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vpkuhus %0,%1,%2"
[(set_attr "type" "vecperm")])
***************
*** 14841,14847 ****
(define_insn "altivec_vpkshus"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 101))]
"TARGET_ALTIVEC"
"vpkshus %0,%1,%2"
[(set_attr "type" "vecperm")])
--- 14856,14863 ----
(define_insn "altivec_vpkshus"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 101))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vpkshus %0,%1,%2"
[(set_attr "type" "vecperm")])
***************
*** 14849,14855 ****
(define_insn "altivec_vpkuwus"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 102))]
"TARGET_ALTIVEC"
"vpkuwus %0,%1,%2"
[(set_attr "type" "vecperm")])
--- 14865,14872 ----
(define_insn "altivec_vpkuwus"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 102))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vpkuwus %0,%1,%2"
[(set_attr "type" "vecperm")])
***************
*** 14857,14863 ****
(define_insn "altivec_vpkswus"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 103))]
"TARGET_ALTIVEC"
"vpkswus %0,%1,%2"
[(set_attr "type" "vecperm")])
--- 14874,14881 ----
(define_insn "altivec_vpkswus"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 103))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vpkswus %0,%1,%2"
[(set_attr "type" "vecperm")])
***************
*** 15033,15039 ****
(define_insn "altivec_vsububs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 125))]
"TARGET_ALTIVEC"
"vsububs %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 15051,15058 ----
(define_insn "altivec_vsububs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 125))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsububs %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 15041,15047 ****
(define_insn "altivec_vsubsbs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 126))]
"TARGET_ALTIVEC"
"vsubsbs %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 15060,15067 ----
(define_insn "altivec_vsubsbs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 126))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsubsbs %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 15049,15055 ****
(define_insn "altivec_vsubuhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 127))]
"TARGET_ALTIVEC"
"vsubuhs %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 15069,15076 ----
(define_insn "altivec_vsubuhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 127))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsubuhs %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 15057,15063 ****
(define_insn "altivec_vsubshs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 128))]
"TARGET_ALTIVEC"
"vsubshs %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 15078,15085 ----
(define_insn "altivec_vsubshs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 128))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsubshs %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 15065,15071 ****
(define_insn "altivec_vsubuws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 129))]
"TARGET_ALTIVEC"
"vsubuws %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 15087,15094 ----
(define_insn "altivec_vsubuws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 129))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsubuws %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 15073,15079 ****
(define_insn "altivec_vsubsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 130))]
"TARGET_ALTIVEC"
"vsubsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 15096,15103 ----
(define_insn "altivec_vsubsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 130))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsubsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
***************
*** 15081,15087 ****
(define_insn "altivec_vsum4ubs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 131))]
"TARGET_ALTIVEC"
"vsum4ubs %0,%1,%2"
[(set_attr "type" "veccomplex")])
--- 15105,15112 ----
(define_insn "altivec_vsum4ubs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 131))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsum4ubs %0,%1,%2"
[(set_attr "type" "veccomplex")])
***************
*** 15089,15095 ****
(define_insn "altivec_vsum4sbs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 132))]
"TARGET_ALTIVEC"
"vsum4sbs %0,%1,%2"
[(set_attr "type" "veccomplex")])
--- 15114,15121 ----
(define_insn "altivec_vsum4sbs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 132))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsum4sbs %0,%1,%2"
[(set_attr "type" "veccomplex")])
***************
*** 15097,15103 ****
(define_insn "altivec_vsum4shs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 133))]
"TARGET_ALTIVEC"
"vsum4shs %0,%1,%2"
[(set_attr "type" "veccomplex")])
--- 15123,15130 ----
(define_insn "altivec_vsum4shs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 133))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsum4shs %0,%1,%2"
[(set_attr "type" "veccomplex")])
***************
*** 15105,15111 ****
(define_insn "altivec_vsum2sws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 134))]
"TARGET_ALTIVEC"
"vsum2sws %0,%1,%2"
[(set_attr "type" "veccomplex")])
--- 15132,15139 ----
(define_insn "altivec_vsum2sws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 134))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsum2sws %0,%1,%2"
[(set_attr "type" "veccomplex")])
***************
*** 15113,15119 ****
(define_insn "altivec_vsumsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 135))]
"TARGET_ALTIVEC"
"vsumsws %0,%1,%2"
[(set_attr "type" "veccomplex")])
--- 15141,15148 ----
(define_insn "altivec_vsumsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 135))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vsumsws %0,%1,%2"
[(set_attr "type" "veccomplex")])
***************
*** 15262,15268 ****
(define_insn "altivec_vctuxs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")] 153))]
"TARGET_ALTIVEC"
"vctuxs %0, %1, %2"
[(set_attr "type" "vecfloat")])
--- 15291,15298 ----
(define_insn "altivec_vctuxs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")] 153))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vctuxs %0, %1, %2"
[(set_attr "type" "vecfloat")])
***************
*** 15270,15276 ****
(define_insn "altivec_vctsxs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")] 154))]
"TARGET_ALTIVEC"
"vctsxs %0, %1, %2"
[(set_attr "type" "vecfloat")])
--- 15300,15307 ----
(define_insn "altivec_vctsxs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
! (match_operand:QI 2 "immediate_operand" "i")] 154))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
"vctsxs %0, %1, %2"
[(set_attr "type" "vecfloat")])
***************
*** 15493,15506 ****
[(set_attr "type" "veccmp")])
(define_insn "altivec_mtvscr"
! [(unspec_volatile [(match_operand:V4SI 0 "register_operand" "v")] 186)]
"TARGET_ALTIVEC"
"mtvscr %0"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_mfvscr"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec_volatile:V8HI [(const_int 0)] 187))]
"TARGET_ALTIVEC"
"mfvscr %0"
[(set_attr "type" "vecsimple")])
--- 15524,15539 ----
[(set_attr "type" "veccmp")])
(define_insn "altivec_mtvscr"
! [(set (reg:SI 110)
! (unspec_volatile:SI
! [(match_operand:V4SI 0 "register_operand" "v")] 186))]
"TARGET_ALTIVEC"
"mtvscr %0"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_mfvscr"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec_volatile:V8HI [(reg:SI 110)] 187))]
"TARGET_ALTIVEC"
"mfvscr %0"
[(set_attr "type" "vecsimple")])