This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: Fix Sparc shift optimization
From: Richard Henderson <rth@redhat.com>
Date: Mon, 6 May 2002 13:20:45 -0700
Incidentally, this test:
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
is redundant with both "I" and SHIFT_COUNT_TRUNCATED.
Fixed as follows on the mainline:
2002-05-06 David S. Miller <davem@redhat.com>
* config/sparc/sparc.md (shift insns): Do not mask off
second operand, 'I' constraint and SHIFT_COUNT_TRUNCATED
take care of it.
--- config/sparc/sparc.md.~1~ Sun May 5 16:05:00 2002
+++ config/sparc/sparc.md Mon May 6 14:25:54 2002
@@ -7234,24 +7234,20 @@
;;- arithmetic shift instructions
(define_insn "ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
if (operands[2] == const1_rtx)
return \"add\\t%1, %1, %0\";
return \"sll\\t%1, %2, %0\";
}"
[(set (attr "type")
(if_then_else (match_operand 2 "const1_operand" "")
(const_string "ialu") (const_string "shift")))])
(define_expand "ashldi3"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -7269,24 +7265,20 @@
}
}")
(define_insn "*ashldi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
"*
{
- if (GET_CODE (operands[2]) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
if (operands[2] == const1_rtx)
return \"add\\t%1, %1, %0\";
return \"sllx\\t%1, %2, %0\";
}"
[(set (attr "type")
(if_then_else (match_operand 2 "const1_operand" "")
(const_string "ialu") (const_string "shift")))])
;; XXX UGH!
(define_insn "ashldi3_v8plus"
@@ -7337,24 +7329,20 @@
"addcc\\t%1, %1, %0"
[(set_attr "type" "compare")])
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
return \"sra\\t%1, %2, %0\";
}"
[(set_attr "type" "shift")])
(define_insn "*ashrsi3_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "r"))))]
"TARGET_ARCH64"
"sra\\t%1, %2, %0"
@@ -7398,24 +7386,20 @@
}
}")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
"*
{
- if (GET_CODE (operands[2]) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
return \"srax\\t%1, %2, %0\";
}"
[(set_attr "type" "shift")])
;; XXX
(define_insn "ashrdi3_v8plus"
[(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
(ashiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
(match_operand:SI 2 "arith_operand" "rI,rI,rI")))
(clobber (match_scratch:SI 3 "=X,X,&h"))]
@@ -7424,24 +7408,20 @@
[(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-
return \"srl\\t%1, %2, %0\";
}"
[(set_attr "type" "shift")])
;; This handles the case where
;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
;; but combiner "simplifies" it for us.
(define_insn "*lshrsi3_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
@@ -7495,24 +7475,20 @@
}
}")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
"*
{
- if (GET_CODE (operands[2]) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
-
return \"srlx\\t%1, %2, %0\";
}"
[(set_attr "type" "shift")])
;; XXX
(define_insn "lshrdi3_v8plus"
[(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
(lshiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
(match_operand:SI 2 "arith_operand" "rI,rI,rI")))
(clobber (match_scratch:SI 3 "=X,X,&h"))]