Re: Patch to decrease time of building minimal delay issue table for the DFA scheduler

[Jan Hubicka <jh at suse dot cz>]

> Jan Hubicka wrote:
> 
> > >  In message <20020503225832.GI23248@atrey.karlin.mff.cuni.cz>, Jan Hubicka
> > > writes:
> > >  > Just curious, how large is resulting insn-attrtab file?
> > >  > In my experiments large genattrtab times just signalized large files so
> > >  > I split the automatons.  You will probably find usefull to model decoders,
> > >  > ieu and fp as separate beasts.
> > > The DFA will eventually be factored and simplified.  RIght now the point
> > > behind that particular DFA is to 100% model the existing pipeline description
> > > for the PPro/P2/P3.
> > Hmm, does splitting of automatons affect the scheduling somewhat?
> > I believe that the old scheduler units are independent, so if you use separate
> > automaton for each unit (in old sense, not new one), it should still result in
> > same schedule, or am I missing something?
> 
>    The splitting automata should not affect on the result insn schedules.  It
> affects only on size of the result tables.  It also makes function
> state_transition slightly slower because to check possibility of insn issue the
> code checks more automata.  You should not be afraid to have many automata (e.g.
> use separate automata for each subtarget) because the code checks only automata to
> which the units of the insn reservation belong.  So if the insn reservation
> contains two units belonging different automata, the code will check only the two
> different automata even if the .md file contains hundred automata.
> 
>   There is also one constraint, if the units mentioned in
> exclusion_set/presence_set/absence_set, they should belong the same automata.  The
> genautomata.c always checks this.

Thanks for clarification.  Whats about if I write the dependence by hand, like
allocation string

(unit1+unit3)|(unit2+unit4)

and give each unit separate automaton?  Is the interference between the
automatons ensured somehow (like that instruction must use unit3 when unit2 or
unit4 is busy)?

Another interesting problem I run into with pentium.  Pentium has two decoders
and it attempts to feed both of them if possible. When is suceeds it resolves
the memory dependancies.  When the instructions are dependent, the second
instruction is stalled and then instruction follows by fetching next pair
later.
My scheduler model resolves this by executing the first instruction inpaired
and pair second instruction with third (after the memory dependency is
resolved).  This reuslts in better schedule, but chip won't execute it without
explicit nop in the way.
Is there any (convenient) way to describe this?  If not I will just ignore
it as it is not really important.

Honza
> 
> Vlad
>