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AMD Athlon DFA description
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, law at cygnus dot com, patches at x86-64 dot org
- Date: Sat, 4 May 2002 00:08:24 +0200
- Subject: AMD Athlon DFA description
Hi,
the attached patch implements DFA scheduling for AMD Athlon.
Once I stabilize the CFG branch, I will install it there so it will
get benchmarked for SPEC benchmark. I will send incremental patch
for pentium shortly.
Honza
Sat May 4 00:04:13 CEST 2002 Jan Hubicka <jh@suse.cz>
* i386.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define
(ix86_use_dfa_pipeline_interface): New function.
(ix86_adjust_cost): Simplify handling of AMD Athlon chip.
* i386.md: Rewrite athlon scheduling description into
DFA form.
*** i386.c Fri May 3 22:48:47 2002
--- dfa/config/i386/i386.c Thu May 2 23:30:09 2002
*************** static char internal_label_prefix[16];
*** 647,652 ****
--- 647,653 ----
static int internal_label_prefix_len;
static int local_symbolic_operand PARAMS ((rtx, enum machine_mode));
+ static int ix86_use_dfa_pipeline_interface PARAMS ((void));
static void output_pic_addr_const PARAMS ((FILE *, rtx, int));
static void put_condition_code PARAMS ((enum rtx_code, enum machine_mode,
int, int, FILE *));
*************** static enum x86_64_reg_class merge_class
*** 766,771 ****
--- 767,774 ----
enum x86_64_reg_class));
/* Initialize the GCC target structure. */
+ #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+ #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ix86_use_dfa_pipeline_interface
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
#ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
*************** ix86_adjust_cost (insn, link, dep_insn,
*** 10241,10265 ****
memory = get_attr_memory (insn);
dep_memory = get_attr_memory (dep_insn);
! if (dep_memory == MEMORY_LOAD || dep_memory == MEMORY_BOTH)
! {
! if (dep_insn_type == TYPE_IMOV || dep_insn_type == TYPE_FMOV)
! cost += 2;
! else
! cost += 3;
! }
/* Show ability of reorder buffer to hide latency of load by executing
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
&& !ix86_agi_dependant (insn, dep_insn, insn_type))
{
! /* Claim moves to take one cycle, as core can issue one load
! at time and the next load can start cycle later. */
! if (dep_insn_type == TYPE_IMOV
! || dep_insn_type == TYPE_FMOV)
! cost = 0;
! else if (cost >= 3)
cost -= 3;
else
cost = 0;
--- 10246,10261 ----
memory = get_attr_memory (insn);
dep_memory = get_attr_memory (dep_insn);
! if (GET_CODE (dep_insn) == JUMP_INSN || GET_CODE (dep_insn) == CALL_INSN)
! return 0;
!
/* Show ability of reorder buffer to hide latency of load by executing
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
&& !ix86_agi_dependant (insn, dep_insn, insn_type))
{
! if (cost >= 3)
cost -= 3;
else
cost = 0;
*************** ix86_adjust_cost (insn, link, dep_insn,
*** 10272,10277 ****
--- 10268,10281 ----
return cost;
}
+ static int
+ ix86_use_dfa_pipeline_interface ()
+ {
+ if (TARGET_ATHLON)
+ return 1;
+ return 0;
+ }
+
static union
{
struct ppro_sched_data
*** i386.md Fri May 3 13:20:56 2002
--- dfa/config/i386/i386.md Sat May 4 00:02:37 2002
***************
*** 867,1030 ****
(const_string "vector")]
(const_string "direct")))
! (define_function_unit "athlon_vectordec" 1 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "athlon_decode" "vector"))
! 1 1)
!
! (define_function_unit "athlon_directdec" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "athlon_decode" "direct"))
! 1 1)
!
! (define_function_unit "athlon_vectordec" 1 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "athlon_decode" "direct"))
! 1 1 [(eq_attr "athlon_decode" "vector")])
!
! (define_function_unit "athlon_ieu" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
! 1 1)
!
! (define_function_unit "athlon_ieu" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "str"))
! 15 15)
!
! (define_function_unit "athlon_ieu" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "imul"))
! 5 0)
!
! (define_function_unit "athlon_ieu" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "idiv"))
! 42 0)
!
! (define_function_unit "athlon_muldiv" 1 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "imul"))
! 5 0)
!
! (define_function_unit "athlon_muldiv" 1 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "idiv"))
! 42 42)
!
! (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
! (cond [(eq_attr "type" "fop,fcmp,fistp")
! (const_string "add")
! (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
! (const_string "mul")
! (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
! (const_string "store")
! (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
! (const_string "any")
! (and (eq_attr "type" "fmov")
! (ior (match_operand:SI 1 "register_operand" "")
! (match_operand 1 "immediate_operand" "")))
! (const_string "store")
! (eq_attr "type" "fmov")
! (const_string "muladd")]
! (const_string "none")))
!
! ;; We use latencies 1 for definitions. This is OK to model colisions
! ;; in execution units. The real latencies are modeled in the "fp" pipeline.
!
! ;; fsin, fcos: 96-192
! ;; fsincos: 107-211
! ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
! (define_function_unit "athlon_fp" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fpspc"))
! 100 1)
!
! ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
! (define_function_unit "athlon_fp" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fdiv"))
! 24 1)
!
! (define_function_unit "athlon_fp" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fop,fmul,fistp"))
! 4 1)
!
! ;; XFmode loads are slow.
! ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
! ;; there are no dependent instructions.
!
! (define_function_unit "athlon_fp" 3 0
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fmov")
! (and (eq_attr "memory" "load")
! (eq_attr "mode" "XF"))))
! 10 1)
!
! (define_function_unit "athlon_fp" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fmov,fsgn"))
! 2 1)
!
! ;; fcmp and ftst instructions
! (define_function_unit "athlon_fp" 3 0
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fcmp")
! (eq_attr "athlon_decode" "direct")))
! 3 1)
!
! ;; fcmpi instructions.
! (define_function_unit "athlon_fp" 3 0
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fcmp")
! (eq_attr "athlon_decode" "vector")))
! 3 1)
!
! (define_function_unit "athlon_fp" 3 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fcmov"))
! 7 1)
!
! (define_function_unit "athlon_fp_mul" 1 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "athlon_fpunits" "mul"))
! 1 1)
!
! (define_function_unit "athlon_fp_add" 1 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "athlon_fpunits" "add"))
! 1 1)
!
! (define_function_unit "athlon_fp_muladd" 2 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "athlon_fpunits" "muladd,mul,add"))
! 1 1)
!
! (define_function_unit "athlon_fp_store" 1 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "athlon_fpunits" "store"))
! 1 1)
!
! ;; We don't need to model the Address Generation Unit, since we don't model
! ;; the re-order buffer yet and thus we never schedule more than three operations
! ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
! ;; decoders independently on the functional units.
!
! ;(define_function_unit "athlon_agu" 3 0
! ; (and (eq_attr "cpu" "athlon")
! ; (and (eq_attr "memory" "!none")
! ; (eq_attr "athlon_fpunits" "none")))
! ; 1 1)
!
! ;; Model load unit to avoid too long sequences of loads. We don't need to
! ;; model store queue, since it is hardly going to be bottleneck.
!
! (define_function_unit "athlon_load" 2 0
! (and (eq_attr "cpu" "athlon")
! (eq_attr "memory" "load,both"))
! 1 1)
!
;; Compare instructions.
--- 867,1269 ----
(const_string "vector")]
(const_string "direct")))
! ;;
! ;; decode0 decode1 decode2
! ;; \ | /
! ;; instruction control unit (72 entry scheduler)
! ;; | |
! ;; integer scheduler (18) stack map
! ;; / | | | | \ stack rename
! ;; ieu0 agu0 ieu1 agu1 ieu2 agu2 scheduler
! ;; | agu0 | agu1 agu2 register file
! ;; | \ | | / | | |
! ;; \ /\ | / fadd fmul fstore
! ;; \ / \ | / fadd fmul fstore
! ;; imul load/store (2x) fadd fmul fstore
!
! (define_automaton "athlon,athlon_mult,athlon_fp")
! (define_cpu_unit "athlon-decode0" "athlon")
! (define_cpu_unit "athlon-decode1" "athlon")
! (define_cpu_unit "athlon-decode2" "athlon")
! (define_reservation "athlon-vector" "(athlon-decode0 + athlon-decode1
! + athlon-decode2)")
! (define_reservation "athlon-direct" "(athlon-decode0 | athlon-decode1
! | athlon-decode2)")
!
! ;; Agu and ieu unit results in extremly large automatons and
! ;; in our approximation they are hardly filled in. Only ieu
! ;; unit can, as issue rate is 3 and agu unit is always used
! ;; first in the insn reservations. Skip the models.
!
! ;(define_cpu_unit "athlon-ieu0" "athlon_ieu")
! ;(define_cpu_unit "athlon-ieu1" "athlon_ieu")
! ;(define_cpu_unit "athlon-ieu2" "athlon_ieu")
! ;(define_reservation "athlon-ieu" "(athlon-ieu0 | athlon-ieu1 | athlon-ieu2)")
! (define_reservation "athlon-ieu" "nothing")
! ;(define_cpu_unit "athlon-agu0" "athlon_agu")
! ;(define_cpu_unit "athlon-agu1" "athlon_agu")
! ;(define_cpu_unit "athlon-agu2" "athlon_agu")
! ;(define_reservation "athlon-agu" "(athlon-agu0 | athlon-agu1 | athlon-agu2)")
! (define_reservation "athlon-agu" "nothing")
!
! (define_cpu_unit "athlon-mult" "athlon_mult")
!
! (define_cpu_unit "athlon-load0" "athlon")
! (define_cpu_unit "athlon-load1" "athlon")
! (define_reservation "athlon-load" "athlon-agu,
! nothing,
! (athlon-load0 | athlon-load1)")
! (define_reservation "athlon-store" "nothing")
!
! ;; The three fp units are fully pipelined with latency of 3
! (define_cpu_unit "athlon-fadd" "athlon_fp")
! (define_cpu_unit "athlon-fmul" "athlon_fp")
! (define_cpu_unit "athlon-fstore" "athlon_fp")
! (define_reservation "athlon-fany" "(athlon-fadd | athlon-fmul | athlon-fstore)")
! (define_reservation "athlon-faddmul" "(athlon-fadd | athlon-fmul)")
!
!
! ;; Latency of push operation is 3 cycles, but ESP value is available
! ;; earlier
! (define_insn_reservation "athlon_push" 2
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "push"))
! "athlon-direct,nothing,athlon-store")
! (define_insn_reservation "athlon_pop" 4
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "push"))
! "athlon-direct,athlon-ieu,athlon-load")
! (define_insn_reservation "athlon_leave" 3
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "push"))
! "athlon-vector,athlon-load")
!
! ;; Lea executes in AGU unit with 2 cycles latency.
! (define_insn_reservation "athlon_lea" 2
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "lea"))
! "athlon-direct,athlon-agu,nothing")
!
! ;; Mul executes in special multiplier unit attached to IEU0
! (define_insn_reservation "athlon_imul" 5
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "imul")
! (eq_attr "memory" "none")))
! "athlon-vector,athlon-ieu+athlon-mult,nothing,nothing,athlon-ieu")
! (define_insn_reservation "athlon_imul_mem" 8
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "imul")
! (eq_attr "memory" "load,both")))
! "athlon-direct,athlon-load,athlon-ieu,athlon-mult,nothing,nothing,athlon-ieu")
! (define_insn_reservation "athlon_idiv" 42
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "idiv")
! (eq_attr "memory" "none")))
! "athlon-direct,athlon-ieu,athlon-mult*41")
! (define_insn_reservation "athlon_idiv_mem" 45
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "idiv")
! (eq_attr "memory" "load,both")))
! "athlon-direct,athlon-load,athlon-ieu,athlon-mult*41")
! (define_insn_reservation "athlon_str" 15
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "str")
! (eq_attr "memory" "load,both")))
! "athlon-direct,athlon-load,athlon-ieu,athlon-mult*10")
!
!
!
! (define_insn_reservation "athlon_idirect" 1
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "direct")
! (and (eq_attr "unit" "integer,unknown")
! (eq_attr "memory" "none"))))
! "athlon-direct,athlon-ieu")
! (define_insn_reservation "athlon_ivector" 2
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "vector")
! (and (eq_attr "unit" "integer,unknown")
! (eq_attr "memory" "none"))))
! "athlon-vector,athlon-ieu,athlon-ieu")
! (define_insn_reservation "athlon_idirect_loadmov" 3
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "imov")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-load")
! (define_insn_reservation "athlon_idirect_load" 4
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "direct")
! (and (eq_attr "unit" "integer,unknown")
! (eq_attr "memory" "load"))))
! "athlon-direct,athlon-load,athlon-ieu")
! (define_insn_reservation "athlon_ivector_load" 6
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "vector")
! (and (eq_attr "unit" "integer,unknown")
! (eq_attr "memory" "load"))))
! "athlon-vector,athlon-load,athlon-ieu,athlon-ieu")
! (define_insn_reservation "athlon_idirect_movstore" 3
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "imov")
! (eq_attr "memory" "store")))
! "athlon-direct,athlon-store")
! (define_insn_reservation "athlon_idirect_both" 4
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "direct")
! (and (eq_attr "unit" "integer,unknown")
! (eq_attr "memory" "both"))))
! "athlon-direct,athlon-load,athlon-ieu,
! athlon-store")
! (define_insn_reservation "athlon_ivector_both" 6
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "vector")
! (and (eq_attr "unit" "integer,unknown")
! (eq_attr "memory" "both"))))
! "athlon-vector,athlon-load,athlon-ieu,athlon-ieu,
! athlon-store")
! (define_insn_reservation "athlon_idirect_store" 1
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "direct")
! (and (eq_attr "unit" "integer,unknown")
! (eq_attr "memory" "store"))))
! "athlon-direct,athlon-ieu,
! athlon-store")
! (define_insn_reservation "athlon_ivector_store" 2
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "vector")
! (and (eq_attr "unit" "integer,unknown")
! (eq_attr "memory" "store"))))
! "athlon-vector,athlon-ieu,athlon-ieu,
! athlon-store")
!
! ;; Athlon floatin point unit
! (define_insn_reservation "athlon_fldxf" 12
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fmov")
! (and (eq_attr "memory" "load")
! (eq_attr "mode" "XF"))))
! "athlon-vector,athlon-fany")
! (define_insn_reservation "athlon_fld" 6
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fmov")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-fany,nothing,athlon-load")
! (define_insn_reservation "athlon_fstxf" 10
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fmov")
! (and (eq_attr "memory" "store,both")
! (eq_attr "mode" "XF"))))
! "athlon-vector,athlon-fstore")
! (define_insn_reservation "athlon_fst" 4
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fmov")
! (eq_attr "memory" "store,both")))
! "athlon-direct,athlon-fstore,nothing,athlon-store")
! (define_insn_reservation "athlon_fist" 4
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fistp"))
! "athlon-direct,athlon-fstore,nothing")
! (define_insn_reservation "athlon_fmov" 2
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fmov"))
! "athlon-direct,athlon-faddmul")
! (define_insn_reservation "athlon_fadd_load" 7
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fop")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-load,athlon-fadd")
! (define_insn_reservation "athlon_fadd" 4
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fop"))
! "athlon-direct,athlon-fadd")
! (define_insn_reservation "athlon_fmul_load" 7
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fmul")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_fmul" 4
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fmul"))
! "athlon-direct,athlon-fmul")
! (define_insn_reservation "athlon_fsgn" 2
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fsgn"))
! "athlon-direct,athlon-fmul")
! (define_insn_reservation "athlon_fdiv_load" 24
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fdiv")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_fdiv" 24
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fdiv"))
! "athlon-direct,athlon-fmul")
! (define_insn_reservation "athlon_fpspc_load" 103
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fpspc")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_fpspc" 100
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fpspc"))
! "athlon-direct,athlon-fmul")
! (define_insn_reservation "athlon_fcmov_load" 10
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fcmov")
! (eq_attr "memory" "load")))
! "athlon-vector,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_fcmov" 7
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fcmov"))
! "athlon-vector,athlon-fmul")
! (define_insn_reservation "athlon_fcomi_load" 6
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fcmp")
! (and (eq_attr "athlon_decode" "vector")
! (eq_attr "memory" "load"))))
! "athlon-vector,athlon-load,athlon-fadd")
! (define_insn_reservation "athlon_fcomi" 3
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "athlon_decode" "vector")
! (eq_attr "type" "fcmp")))
! "athlon-vector,athlon-fadd")
! (define_insn_reservation "athlon_fcom_load" 5
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "fcmp")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-load,athlon-fadd")
! (define_insn_reservation "athlon_fcom" 2
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fcmp"))
! "athlon-direct,athlon-fadd")
! (define_insn_reservation "athlon_fxch" 2
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fxch"))
! "athlon-direct,athlon-fany")
! ;; Athlon handle MMX operations in the FPU unit with shorter latencies
! (define_insn_reservation "athlon_mmxsseld" 4
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "mmxmov,ssemov")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-fany,athlon-load")
! (define_insn_reservation "athlon_mmxssest" 2
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "mmxmov,ssemov")
! (eq_attr "memory" "store,both")))
! "athlon-direct,athlon-store")
! (define_insn_reservation "athlon_mmxssemov" 2
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "mmxmov,ssemov"))
! "athlon-direct,athlon-faddmul")
! (define_insn_reservation "athlon_mmxmul_load" 6
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "mmxmul")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_mmxmul" 3
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "mmxmul"))
! "athlon-direct,athlon-fmul")
! (define_insn_reservation "athlon_mmx_load" 5
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "unit" "mmx")
! (eq_attr "memory" "load")))
! "athlon-direct,athlon-load,athlon-faddmul")
! (define_insn_reservation "athlon_mmx" 2
! (and (eq_attr "cpu" "athlon")
! (eq_attr "unit" "mmx"))
! "athlon-direct,athlon-faddmul")
! ;; SSE operations are handled by the i387 unit as well. The latnecy
! ;; is same as for i387 operations for scalar operations
! (define_insn_reservation "athlon_sselog_load" 6
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "sselog")
! (eq_attr "memory" "load")))
! "athlon-vector,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_sselog" 3
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "sselog"))
! "athlon-vector,athlon-fmul")
! (define_insn_reservation "athlon_ssecmp_load" 5
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssecmp")
! (and (eq_attr "mode" "SF,DF")
! (eq_attr "memory" "load"))))
! "athlon-vector,athlon-load,athlon-fadd")
! (define_insn_reservation "athlon_ssecmp" 2
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssecmp")
! (eq_attr "mode" "SF,DF")))
! "athlon-direct,athlon-fadd")
! (define_insn_reservation "athlon_ssecmpvector_load" 6
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssecmp")
! (eq_attr "memory" "load")))
! "athlon-vector,athlon-fadd")
! (define_insn_reservation "athlon_ssecmpvector" 3
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "ssecmp"))
! "athlon-vector,athlon-fadd")
! (define_insn_reservation "athlon_sseadd_load" 7
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "sseadd")
! (and (eq_attr "mode" "SF,DF")
! (eq_attr "memory" "load"))))
! "athlon-direct,athlon-load,athlon-fadd")
! (define_insn_reservation "athlon_sseadd" 4
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "sseadd")
! (eq_attr "mode" "SF,DF")))
! "athlon-direct,athlon-fadd")
! (define_insn_reservation "athlon_sseaddvector_load" 8
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "sseadd")
! (eq_attr "memory" "load")))
! "athlon-vector,athlon-load,athlon-fadd")
! (define_insn_reservation "athlon_sseaddvector" 5
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "sseadd"))
! "athlon-vector,athlon-fadd")
! (define_insn_reservation "athlon_ssemul_load" 7
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssemul")
! (and (eq_attr "mode" "SF,DF")
! (eq_attr "memory" "load"))))
! "athlon-direct,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_ssemul" 4
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssemul")
! (eq_attr "mode" "SF,DF")))
! "athlon-direct,athlon-fmul")
! (define_insn_reservation "athlon_ssemulvector_load" 8
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssemul")
! (eq_attr "memory" "load")))
! "athlon-vector,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_ssemulvector" 5
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "ssemul"))
! "athlon-vector,athlon-fmul")
! (define_insn_reservation "athlon_ssediv_load" 19
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssediv")
! (and (eq_attr "mode" "SF,DF")
! (eq_attr "memory" "load"))))
! "athlon-direct,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_ssediv" 16
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssediv")
! (eq_attr "mode" "SF,DF")))
! "athlon-direct,athlon-fmul")
! (define_insn_reservation "athlon_ssedivvector_load" 32
! (and (eq_attr "cpu" "athlon")
! (and (eq_attr "type" "ssediv")
! (eq_attr "memory" "load")))
! "athlon-vector,athlon-load,athlon-fmul")
! (define_insn_reservation "athlon_ssedivvector" 29
! (and (eq_attr "cpu" "athlon")
! (eq_attr "type" "ssediv"))
! "athlon-vector,athlon-fmul")
;; Compare instructions.