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[PATCH] Fix PR target/6512 and PR target/5628 (take 2)
- From: Jakub Jelinek <jakub at redhat dot com>
- To: mark at codesourcery dot com, rth at redhat dot com, davem at redhat dot com
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Wed, 1 May 2002 10:36:45 +0200
- Subject: [PATCH] Fix PR target/6512 and PR target/5628 (take 2)
- References: <20020430141905.Q32482@sunsite.ms.mff.cuni.cz> <20020430123112.A2987@redhat.com> <20020430.151235.38070054.davem@redhat.com> <20020430185018.Y23056@devserv.devel.redhat.com>
- Reply-to: Jakub Jelinek <jakub at redhat dot com>
Hi!
I've commited following fix for the two SPARC PRs to trunk (bootstrapped
on sparc-redhat-linux (or should that be sparc-aurora-linux?), no regressions).
It is a regression from at least gcc 2.96-RH (don't have other pre-gcc-3.1
compilers on my SPARC box).
Mark, ok for branch?
2002-05-01 Jakub Jelinek <jakub@redhat.com>
PR target/6512, PR target/5628
* config/sparc/sparc.md (movdf_insn_v9only_novis): Don't allow >= %f32
when memory is not aligned.
(movdf_insn_v9only_vis): Likewise.
* config/sparc/sparc.h (SECONDARY_INPUT_RELOAD_CLASS): Request a FP_REGS
temporary for EXTRA_FP_REGS DFmode load from unaligned memory.
(SECONDARY_OUTPUT_RELOAD_CLASS): Similarly.
--- gcc/config/sparc/sparc.md.jj Tue Apr 30 22:05:20 2002
+++ gcc/config/sparc/sparc.md Tue Apr 30 22:05:27 2002
@@ -3349,8 +3349,8 @@
;; We have available v9 double floats but not 64-bit
;; integer registers and no VIS.
(define_insn "*movdf_insn_v9only_novis"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,e,*r,o")
- (match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGe"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,f,*r,o")
+ (match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGf"))]
"TARGET_FPU
&& TARGET_V9
&& ! TARGET_VIS
@@ -3375,8 +3375,8 @@
;; We have available v9 double floats but not 64-bit
;; integer registers but we have VIS.
(define_insn "*movdf_insn_v9only_vis"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,e,*r,o")
- (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGe"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o")
+ (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))]
"TARGET_FPU
&& TARGET_VIS
&& ! TARGET_ARCH64
--- gcc/config/sparc/sparc.h.jj Tue Apr 30 22:05:20 2002
+++ gcc/config/sparc/sparc.h Tue Apr 30 22:28:46 2002
@@ -1426,7 +1426,10 @@ extern const char leaf_reg_remap[];
We need a temporary when loading/storing a HImode/QImode value
between memory and the FPU registers. This can happen when combine puts
- a paradoxical subreg in a float/fix conversion insn. */
+ a paradoxical subreg in a float/fix conversion insn.
+
+ We need a temporary when loading/storing a DFmode value between
+ unaligned memory and the upper FPU registers. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
((FP_REG_CLASS_P (CLASS) \
@@ -1435,28 +1438,36 @@ extern const char leaf_reg_remap[];
|| ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
&& true_regnum (IN) == -1))) \
? GENERAL_REGS \
- : (((TARGET_CM_MEDANY \
- && symbolic_operand ((IN), (MODE))) \
- || (TARGET_CM_EMBMEDANY \
- && text_segment_operand ((IN), (MODE)))) \
- && !flag_pic) \
- ? GENERAL_REGS \
- : NO_REGS)
+ : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
+ && GET_CODE (IN) == MEM && TARGET_ARCH32 \
+ && ! mem_min_alignment ((IN), 8)) \
+ ? FP_REGS \
+ : (((TARGET_CM_MEDANY \
+ && symbolic_operand ((IN), (MODE))) \
+ || (TARGET_CM_EMBMEDANY \
+ && text_segment_operand ((IN), (MODE)))) \
+ && !flag_pic) \
+ ? GENERAL_REGS \
+ : NO_REGS)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
- ((FP_REG_CLASS_P (CLASS) \
+ ((FP_REG_CLASS_P (CLASS) \
&& ((MODE) == HImode || (MODE) == QImode) \
&& (GET_CODE (IN) == MEM \
|| ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
&& true_regnum (IN) == -1))) \
- ? GENERAL_REGS \
- : (((TARGET_CM_MEDANY \
- && symbolic_operand ((IN), (MODE))) \
- || (TARGET_CM_EMBMEDANY \
- && text_segment_operand ((IN), (MODE)))) \
- && !flag_pic) \
- ? GENERAL_REGS \
- : NO_REGS)
+ ? GENERAL_REGS \
+ : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
+ && GET_CODE (IN) == MEM && TARGET_ARCH32 \
+ && ! mem_min_alignment ((IN), 8)) \
+ ? FP_REGS \
+ : (((TARGET_CM_MEDANY \
+ && symbolic_operand ((IN), (MODE))) \
+ || (TARGET_CM_EMBMEDANY \
+ && text_segment_operand ((IN), (MODE)))) \
+ && !flag_pic) \
+ ? GENERAL_REGS \
+ : NO_REGS)
/* On SPARC it is not possible to directly move data between
GENERAL_REGS and FP_REGS. */
Jakub