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IA64 HP-UX Optimization patch
- From: Steve Ellcey <sje at cup dot hp dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 28 Mar 2002 09:26:13 -0800 (PST)
- Subject: IA64 HP-UX Optimization patch
- Reply-to: sje at cup dot hp dot com
This is a patch to make the ILP32 mode on IA64 HP-UX more efficient. It
adds two new instructions to ia64.md which will only be used in ILP32
mode. They are extensions of the existing ptr_extend instruction. They
use a new predicate that I added to ia64.c. Tested on IA64 HP-UX, which
is the only platform that will use these. There is no need to put this
on the 3.1 branch but I would like it reviewed and checked in on the
mainline if possible.
Steve Ellcey
sje@cup.hp.com
2002-03-28 Steve Ellcey <sje@cup.hp.com>
* gcc/config/ia64.md (*ptr_extend_plus_1, *ptr_extend_plus_2):
New versions of ptr_extend.
* gcc/config/ia64.c (basereg_operand): New predicate used in
above instructions.
* gcc/config/ia64-protos.h (basereg_operand): Ditto.
*** gcc.orig/gcc/config/ia64/ia64.md Thu Mar 28 08:12:07 2002
--- gcc/gcc/config/ia64/ia64.md Thu Mar 28 09:11:04 2002
***************
*** 5304,5309 ****
--- 5304,5332 ----
[(set_attr "itanium_class" "ialu")])
;;
+ ;; Optimizations for ptr_extend
+
+ (define_insn "*ptr_extend_plus_1"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (unspec:DI
+ [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
+ (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
+ 24))]
+ ""
+ "addp4 %0 = %2, %1"
+ [(set_attr "itanium_class" "ialu")])
+
+ (define_insn "*ptr_extend_plus_2"
+ [(set (match_operand:DI 0 "gr_register_operand" "=r")
+ (unspec:DI
+ [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
+ (match_operand:SI 2 "basereg_operand" "r"))]
+ 24))]
+ ""
+ "addp4 %0 = %1, %2"
+ [(set_attr "itanium_class" "ialu")])
+
+ ;;
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for EH handling
(define_insn "prologue_use"
*** gcc.orig/gcc/config/ia64/ia64.c Thu Mar 28 08:12:10 2002
--- gcc/gcc/config/ia64/ia64.c Thu Mar 28 08:47:47 2002
*************** tfreg_or_fp01_operand (op, mode)
*** 864,869 ****
--- 864,884 ----
return 0;
return fr_reg_or_fp01_operand (op, mode);
}
+
+ /* Return 1 if OP is valid as a base register in a reg + offset address. */
+
+ int
+ basereg_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+ {
+ /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
+ checks from pa.c basereg_operand as well? Seems to be OK without them
+ in test runs. */
+
+ return (register_operand (op, mode) &&
+ REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
+ }
/* Return 1 if the operands of a move are ok. */
*** gcc.orig/gcc/config/ia64/ia64-protos.h Thu Mar 28 08:43:32 2002
--- gcc/gcc/config/ia64/ia64-protos.h Thu Mar 28 08:44:02 2002
*************** extern int ar_pfs_reg_operand PARAMS((rt
*** 66,71 ****
--- 66,72 ----
extern int general_tfmode_operand PARAMS((rtx, enum machine_mode));
extern int destination_tfmode_operand PARAMS((rtx, enum machine_mode));
extern int tfreg_or_fp01_operand PARAMS((rtx, enum machine_mode));
+ extern int basereg_operand PARAMS((rtx, enum machine_mode));
extern int ia64_move_ok PARAMS((rtx, rtx));
extern int ia64_depz_field_mask PARAMS((rtx, rtx));