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PATCH ARM delete redundant reload patterns for multiply
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard dot Earnshaw at arm dot com
- Date: Tue, 26 Mar 2002 13:54:19 +0000
- Subject: PATCH ARM delete redundant reload patterns for multiply
- Organization: ARM Ltd.
- Reply-to: Richard dot Earnshaw at arm dot com
Some time ago reload was rewritten so that elimination of the frame
pointer wouldn't lead to mangled insn patterns. This patch
garbage-collects a few recognizer patterns that used to be needed to
handle that.
2002-03-26 Richard Earnshaw <rearnsha@arm.com>
* arm.md (reload_mulsi3, reload_mulsi_compare0, reload_muladdsi)
(reload_mulsi_compare0_scratch, reload_muladdsi_compare0)
(reload_muladdsi_compare0_scratch): Delete.
Index: arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.97
diff -p -r1.97 arm.md
*** arm.md 2002/03/25 22:22:35 1.97
--- arm.md 2002/03/26 13:46:07
***************
*** 7011,7149 ****
]
)
- ;; These variants of the above insns can occur if the first operand is the
- ;; frame pointer and we eliminate that. This is a kludge, but there doesn't
- ;; seem to be a way around it. Most of the predicates have to be null
- ;; because the format can be generated part way through reload, so
- ;; if we don't match it as soon as it becomes available, reload doesn't know
- ;; how to reload pseudos that haven't got hard registers; the constraints will
- ;; sort everything out.
-
- (define_insn "*reload_mulsi3"
- [(set (match_operand:SI 0 "" "=&r")
- (plus:SI (plus:SI (match_operator:SI 5 "shift_operator"
- [(match_operand:SI 3 "" "r")
- (match_operand:SI 4 "" "rM")])
- (match_operand:SI 2 "" "r"))
- (match_operand:SI 1 "const_int_operand" "n")))]
- "TARGET_ARM && reload_in_progress"
- "*
- output_asm_insn (\"add%?\\t%0, %2, %3%S5\", operands);
- operands[2] = operands[1];
- operands[1] = operands[0];
- return output_add_immediate (operands);
- "
- [
- ; we have no idea how long the add_immediate is, it could be up to 4.
- (set_attr "length" "20")]
- )
-
- (define_insn "*reload_mulsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (plus:SI
- (plus:SI
- (match_operator:SI 5 "shift_operator"
- [(match_operand:SI 3 "" "r")
- (match_operand:SI 4 "" "rM")])
- (match_operand:SI 1 "" "r"))
- (match_operand:SI 2 "const_int_operand" "n"))
- (const_int 0)))
- (set (match_operand:SI 0 "" "=&r")
- (plus:SI (plus:SI (match_op_dup 5 [(match_dup 3) (match_dup 4)])
- (match_dup 1))
- (match_dup 2)))]
- "TARGET_ARM && reload_in_progress && !arm_is_xscale"
- "*
- output_add_immediate (operands);
- return \"add%?s\\t%0, %0, %3%S5\";
- "
- [(set_attr "conds" "set")
- (set_attr "shift" "3")
- (set_attr "length" "20")]
- )
-
- (define_insn "*reload_mulsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (plus:SI
- (plus:SI
- (match_operator:SI 5 "shift_operator"
- [(match_operand:SI 3 "" "r")
- (match_operand:SI 4 "" "rM")])
- (match_operand:SI 1 "" "r"))
- (match_operand:SI 2 "const_int_operand" "n"))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=&r"))]
- "TARGET_ARM && reload_in_progress && !arm_is_xscale"
- "*
- output_add_immediate (operands);
- return \"add%?s\\t%0, %0, %3%S5\";
- "
- [(set_attr "conds" "set")
- (set_attr "shift" "3")
- (set_attr "length" "20")]
- )
-
- ;; These are similar, but are needed when the mla pattern contains the
- ;; eliminated register as operand 3.
-
- (define_insn "*reload_muladdsi"
- [(set (match_operand:SI 0 "" "=&r,&r")
- (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "" "%0,r")
- (match_operand:SI 2 "" "r,r"))
- (match_operand:SI 3 "" "r,r"))
- (match_operand:SI 4 "const_int_operand" "n,n")))]
- "TARGET_ARM && reload_in_progress"
- "*
- output_asm_insn (\"mla%?\\t%0, %2, %1, %3\", operands);
- operands[2] = operands[4];
- operands[1] = operands[0];
- return output_add_immediate (operands);
- "
- [(set_attr "length" "20")
- (set_attr "type" "mult")]
- )
-
- (define_insn "*reload_muladdsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (plus:SI (plus:SI (mult:SI
- (match_operand:SI 3 "" "r")
- (match_operand:SI 4 "" "r"))
- (match_operand:SI 1 "" "r"))
- (match_operand:SI 2 "const_int_operand" "n"))
- (const_int 0)))
- (set (match_operand:SI 0 "" "=&r")
- (plus:SI (plus:SI (mult:SI (match_dup 3) (match_dup 4)) (match_dup 1))
- (match_dup 2)))]
- "TARGET_ARM && reload_in_progress && !arm_is_xscale"
- "*
- output_add_immediate (operands);
- output_asm_insn (\"mla%?s\\t%0, %3, %4, %0\", operands);
- return \"\";
- "
- [(set_attr "length" "20")
- (set_attr "conds" "set")
- (set_attr "type" "mult")]
- )
-
- (define_insn "*reload_muladdsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (plus:SI (plus:SI (mult:SI
- (match_operand:SI 3 "" "r")
- (match_operand:SI 4 "" "r"))
- (match_operand:SI 1 "" "r"))
- (match_operand:SI 2 "const_int_operand" "n"))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=&r"))]
- "TARGET_ARM && reload_in_progress"
- "*
- output_add_immediate (operands);
- return \"mla%?s\\t%0, %3, %4, %0\";
- "
- [(set_attr "length" "20")
- (set_attr "conds" "set")
- (set_attr "type" "mult")]
- )
-
(define_insn "*and_scc"
--- 7011,7016 ----