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fix alpha ev4 bootstrap
- From: Richard Henderson <rth at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 17 Mar 2002 19:04:12 -0800
- Subject: fix alpha ev4 bootstrap
* config/alpha/alpha.c (alpha_emit_set_const_1): Build add insns
explicitly.
Index: config/alpha/alpha.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.c,v
retrieving revision 1.233.2.2
diff -c -p -d -r1.233.2.2 alpha.c
*** alpha.c 2002/03/15 23:14:58 1.233.2.2
--- alpha.c 2002/03/18 03:02:33
*************** alpha_emit_set_const_1 (target, mode, c,
*** 2267,2273 ****
/* Use a pseudo if highly optimizing and still generating RTL. */
rtx subtarget
= (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
! rtx temp;
#if HOST_BITS_PER_WIDE_INT == 64
/* We are only called for SImode and DImode. If this is SImode, ensure that
--- 2267,2273 ----
/* Use a pseudo if highly optimizing and still generating RTL. */
rtx subtarget
= (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
! rtx temp, insn;
#if HOST_BITS_PER_WIDE_INT == 64
/* We are only called for SImode and DImode. If this is SImode, ensure that
*************** alpha_emit_set_const_1 (target, mode, c,
*** 2317,2328 ****
{
temp = copy_to_suggested_reg (GEN_INT (high << 16), subtarget, mode);
if (extra != 0)
! temp = expand_binop (mode, add_optab, temp, GEN_INT (extra << 16),
! subtarget, 0, OPTAB_WIDEN);
! return expand_binop (mode, add_optab, temp, GEN_INT (low),
! target, 0, OPTAB_WIDEN);
}
}
--- 2317,2343 ----
{
temp = copy_to_suggested_reg (GEN_INT (high << 16), subtarget, mode);
+ /* As of 2002-02-23, addsi3 is only available when not optimizing.
+ This means that if we go through expand_binop, we'll try to
+ generate extensions, etc, which will require new pseudos, which
+ will fail during some split phases. The SImode add patterns
+ still exist, but are not named. So build the insns by hand. */
+
if (extra != 0)
! {
! if (! subtarget)
! subtarget = gen_reg_rtx (mode);
! insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
! insn = gen_rtx_SET (VOIDmode, subtarget, insn);
! emit_insn (insn);
! }
! if (target == NULL)
! target = gen_reg_rtx (mode);
! insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
! insn = gen_rtx_SET (VOIDmode, target, insn);
! emit_insn (insn);
! return target;
}
}