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Test results might have formatting problems for some.
Attaching the txt file with this mail.
> Hi,
>
> > > >> 26th Sept,2001,Naveen Sharma Wrote:
> > > > > I have been interested by the discussion on the new DFA
> > > > based scheduler
> > > > > developed by you for gcc.I plan to study the
> > implementation of the
> > > > > scheduler and would like to contribute further for the
> > scheduler.
> > > > > My friend,Nitin Gupta,would be joining me in the effort.
> > > > > At present we are interested in using the DFA based scheduler
> > > > > for SH4 target which might benefit from the new scheduler.
>
> > I've never worked on SH4. If this is a not OOO processor
> > than you might have an improvement.
>
> We would like to submit DFA pipeline description for SH4 processor.
> We would also like to inform about test results that we have measured
> with this patch.Some benchmarks notably SLALOM
>
> ( http://www.scl.ameslab.gov/Publications/SLALOM/FirstScalable.html)
>
> have shown (12%-13%)improvement.
>
> Meanwhile there are certain applications which have slightly
> degraded performance.We are analysing them and would update
> you regarding them.
>
> On the whole,it seems that there is gain in performance.
>
> Here are the results compared with and without the patch.
>
> Enter the number of seconds that is the goal: 60
> Enter a lower bound for n: 50
> 50 patches:
> Task Seconds Operations MFLOPS % of Time
> Reader 0.028 258 0.009215 12.7 %
> Region 0.001 348 0.348000 0.5 %
> SetUp1 0.033 182283 5.524068 15.0 %
> SetUp2 0.065 350880 5.398486 29.5 %
> SetUp3 0.001 2588 2.588000 0.5 %
> Solver 0.035 131460 3.756208 15.9 %
> Storer 0.059 2400 0.040681 26.8 %
> TOTALS 0.220 670217 3.046635 100.0 %
> Enter an upper bound for n: 700
> ...
>
> 1. GCC Ver 3.1 (With DFA)
>
> Machine: SH4 Processor: SH4
> Memory: 64 MB # of procs: 1
> Cache: 8 KB # used: 1
> Clock: 200 MHz
> OS: QNX6.1 Timer: Wall, gettimeofday()
> Language: C Alone: yes
> Compiler: cc Run by: Naveen Sharma
> Options: -O2 -ml -m4 Date: 19th Dec,2001
> M ops: 326.828 Time: 60.710 seconds
> n: 641 MFLOPS: 5.3834
> Approximate data memory use: 3364768 bytes.
>
> 2. GCC Version 3.1 (Without DFA)
>
> Machine: SH4 Processor: SH4
> Memory: 64 MB # of procs: 1
> Cache: 8 KB # used: 1
> Clock: 200 MHz
> OS: QNX6.1 Timer: Wall, gettimeofday()
> Language: C Alone: yes
> Compiler: cc Run by: Naveen Sharma
> Options: -O2 -ml -m4 Date: 19th Dec,2001
> M ops: 282.899 Time: 59.821 seconds
> n: 608 MFLOPS: 4.7291
> Approximate data memory use: 3031072 bytes.
>
> Additionally we measured timing data for some
> applications.The sumamry is as
> under.(***) are put where data could not be collected for some reason.
>
> --------------------------------------------------------------
> --------------
> --------------
> Benchmark Name options Input Data Size Execution
> Times(seconds)/MFLOPS/KFLOPS
>
> 2.95.2|3.1(without dfa)|3.1(With DFA Patch)
> --------------------------------------------------------------
> --------------
> -----------
>
> 1. SLALOM 60s(Time Target) 4.4445
> 4.7291 5.3834 MFLOPS
> 2. JPEG
>
> COMPRESSION -optimize 2.25 MB 2.71s
> 2.38s
> 2.32s
> -quality 95
>
> --------------------------------------------------------------
> --------------
> ------------
> DE-COMPRESSION
> -bmp 328 KB 2.27s
> *** 2.11s
>
> --------------------------------------------------------------
> --------------
> ------------
> 3. GZIP
>
> COMPRESSION default 80.5 MB 332.03s
> 313.83s 325.22s
>
> --------------------------------------------------------------
> --------------
> -------------
>
> DE_COMPRESSION default 16.2 MB 16.83s
> 17.04s 17.06s
>
> --------------------------------------------------------------
> --------------
> -------------
> 4. GSM
>
> COMPRESSION 289 KB 9.87s
> *** 5.68s
> 1.71 MB ***
> 33.22s 33.18s
>
> --------------------------------------------------------------
> --------------
> -------------
> DE_COMPRESSION 289 KB 3.41s
> ***
> 2.92s
> 361 KB 21.07s
> 19.39s 17.21s
>
> --------------------------------------------------------------
> --------------
> -------------
> 5. LINPACK
>
> ROLLED SINGLE PRECISION ***
> 21130 21870 KFLOPS
> -----------------------
> ROLLED DOUBLE PRECISION ***
> 9631
> 10025 KFLOPS
> -----------------------
> UNROLLED SINGLE PRECISION ***
> 20936
> 21800 KFLOPS
> ---------------------------
> UNROLLED DOUBLE PRECISION ***
> 10114
> 10831 KFLOPS
> --------------------------------------------------------------
> --------------
> ------------
>
>
> Thanks for your co-operation in our effort.
>
> Best Regards,
> Naveen Sharma.
>
> PS: The patch is bootstrapped on Linux successfully.
>
>
> Index: ChangeLog
> ===================================================================
> RCS file: /cvs/gcc/gcc/gcc/ChangeLog,v
> retrieving revision 1.11215.2.12
> diff -c -p -r1.11215.2.12 ChangeLog
> *** ChangeLog 2001/10/28 17:57:48 1.11215.2.12
> --- ChangeLog 2001/12/20 14:03:54
> ***************
> *** 1,3 ****
> --- 1,25 ----
> + 2001-12-20 Naveen Sharma,Nitin Gupta
> <naveens@noida.hcltech.com,niting@noida.hcltech.com>
> +
> + * config/sh/sh.c (sh_use_dfa_interface): New function.
> +
> + (sh_issue_rate): New Function.
> + TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE: define.
> + TARGET_SCHED_ISSUE_RATE: define.
> +
> + * config/sh/sh.md: Add DFA based pipeline description for SH4.
> +
> + (define_attr insn_class): New attribute used for DFA
> + scheduling.
> + (define_insn cmpgtsi_t): Set attribute insn_class mt_group.
> + (cmpgesi_t,cmpgtusi_t,cmpgeusi_t,cmpeqsi_t,
> + cmpeqdi_t): Likewise.
> +
> + (add,addc1,addsi3,subc,subc1,*subsi3_internal,
> + negc,negsi2,ashldi3_k,lshrdi3_k,ashrdi3_k): Set insn_class
> + ex_group.
> + (iorsi3,rotlsi3_1,rotlsi3_31,rotlsi3_16): Likewise.
> +
> +
> 2001-10-03 Vladimir Makarov <vmakarov@toke.toronto.redhat.com>
>
> * haifa-sched.c (queue_to_ready): Remove unnecessary
> condition for
> Index: config/sh/sh.c
> ===================================================================
> RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.c,v
> retrieving revision 1.117.2.1
> diff -c -p -r1.117.2.1 sh.c
> *** sh.c 2001/10/28 18:00:48 1.117.2.1
> --- sh.c 2001/12/20 14:04:36
> *************** static void sh_output_function_epilogue
> *** 162,168 ****
> static void sh_insert_attributes PARAMS ((tree, tree *));
> static void sh_asm_named_section PARAMS ((const char *,
> unsigned int));
> static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
> !
>
> /* Initialize the GCC target structure. */
> #undef TARGET_ATTRIBUTE_TABLE
> #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
> --- 162,172 ----
> static void sh_insert_attributes PARAMS ((tree, tree *));
> static void sh_asm_named_section PARAMS ((const char *,
> unsigned int));
> static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
> !
> !
> ! static int sh_use_dfa_interface PARAMS ((void));
> ! static int sh_issue_rate PARAMS ((void));
> !
> /* Initialize the GCC target structure. */
> #undef TARGET_ATTRIBUTE_TABLE
> #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
> *************** static int sh_adjust_cost PARAMS ((rtx,
> *** 176,181 ****
> --- 180,191 ----
> #undef TARGET_SCHED_ADJUST_COST
> #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
>
> + #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
> + #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
> + sh_use_dfa_interface
> + #undef TARGET_SCHED_ISSUE_RATE
> + #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
> +
> struct gcc_target targetm = TARGET_INITIALIZER;
>
>
> /* Print the operand address in x to the stream. */
> *************** int
> *** 5705,5708 ****
> --- 5715,5741 ----
> sh_pr_n_sets ()
> {
> return REG_N_SETS (PR_REG);
> + }
> +
> + /* This Function Returns non zero if DFA based scheduler
> + interface is to be used.At present supported only for
> + SH4. */
> + int
> + sh_use_dfa_interface()
> + {
> + if (TARGET_SH4)
> + return 1;
> + else
> + return 0;
> + }
> +
> + /* This function returns "2" that signifies dual issue
> + for SH4 processor.To be used by DFA pipeline description. */
> + int
> + sh_issue_rate()
> + {
> + if(TARGET_SH4)
> + return 2;
> + else
> + return 1;
> }
> Index: config/sh/sh.md
> ===================================================================
> RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.md,v
> retrieving revision 1.89
> diff -c -p -r1.89 sh.md
> *** sh.md 2001/08/18 00:53:20 1.89
> --- sh.md 2001/12/20 14:05:43
> ***************
> *** 181,186 ****
> --- 181,208 ----
>
> "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,lo
> ad,load_si,sto
> re,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload
> ,pcload_si,rte
> ,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
> (const_string "other"))
>
> + ;; We define a new attribute namely "insn_class".We use
> + ;; this for DFA based pipeline description.
> + ;; Although the "type" attribute covers almost all insn
> + ;; classes,it is more convenient to define new attribute
> + ;; for certain reservations.
> + ;;
> + ;; mt_group SH4 "mt" group instructions.
> + ;;
> + ;; ex_group SH4 "ex" group instructions.They mostly
> + ;; overlap with arithmetic instructions but
> + ;; new attribute defined to distinguish from
> + ;; mt group instructions.
> + ;;
> + ;; lds_to_fpscr The "type" attribute couldn't sufficiently
> + ;; distinguish it from others.It is part of
> + ;; new attribute.Similar case with ldsmem_to_fpscr
> + ;; and cwb.
> +
> + (define_attr "insn_class"
> + "mt_group,ex_group,lds_to_fpscr,ldsmem_to_fpscr,cwb,none"
> + (const_string "none"))
> +
> ;; Indicate what precision must be selected in fpscr for
> this insn, if
> any.
>
> (define_attr "fp_mode" "single,double,none" (const_string "none"))
> ***************
> *** 607,613 ****
> (match_operand:SI 1 "arith_operand" "L,r"))
> (const_int 0)))]
> ""
> ! "tst %1,%0")
>
> ;; ??? Perhaps should only accept reg/constant if the
> register is reg 0.
> ;; That would still allow reload to create cmpi
> instructions, but would
> --- 629,636 ----
> (match_operand:SI 1 "arith_operand" "L,r"))
> (const_int 0)))]
> ""
> ! "tst %1,%0"
> ! [(set_attr "insn_class" "mt_group")])
>
> ;; ??? Perhaps should only accept reg/constant if the
> register is reg 0.
> ;; That would still allow reload to create cmpi
> instructions, but would
> ***************
> *** 623,629 ****
> "@
> tst %0,%0
> cmp/eq %1,%0
> ! cmp/eq %1,%0")
>
> (define_insn "cmpgtsi_t"
> [(set (reg:SI T_REG)
> --- 646,653 ----
> "@
> tst %0,%0
> cmp/eq %1,%0
> ! cmp/eq %1,%0"
> ! [(set_attr "insn_class" "mt_group,mt_group,mt_group")])
>
> (define_insn "cmpgtsi_t"
> [(set (reg:SI T_REG)
> ***************
> *** 632,638 ****
> ""
> "@
> cmp/gt %1,%0
> ! cmp/pl %0")
>
> (define_insn "cmpgesi_t"
> [(set (reg:SI T_REG)
> --- 656,663 ----
> ""
> "@
> cmp/gt %1,%0
> ! cmp/pl %0"
> ! [(set_attr "insn_class" "mt_group,mt_group")])
>
> (define_insn "cmpgesi_t"
> [(set (reg:SI T_REG)
> ***************
> *** 641,648 ****
> ""
> "@
> cmp/ge %1,%0
> ! cmp/pz %0")
> !
>
> ;;
> --------------------------------------------------------------
> -----------
> ;; SImode unsigned integer comparisons
> ;;
> --------------------------------------------------------------
> -----------
> --- 666,674 ----
> ""
> "@
> cmp/ge %1,%0
> ! cmp/pz %0"
> ! [(set_attr "insn_class" "mt_group,mt_group")])
> !
> ;;
> --------------------------------------------------------------
> -----------
> ;; SImode unsigned integer comparisons
> ;;
> --------------------------------------------------------------
> -----------
> ***************
> *** 652,665 ****
> (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
> (match_operand:SI 1 "arith_reg_operand" "r")))]
> ""
> ! "cmp/hs %1,%0")
>
> (define_insn "cmpgtusi_t"
> [(set (reg:SI T_REG)
> (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
> (match_operand:SI 1 "arith_reg_operand" "r")))]
> ""
> ! "cmp/hi %1,%0")
>
> ;; We save the compare operands in the cmpxx patterns and
> use them when
> ;; we generate the branch.
> --- 678,693 ----
> (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
> (match_operand:SI 1 "arith_reg_operand" "r")))]
> ""
> ! "cmp/hs %1,%0"
> ! [(set_attr "insn_class" "mt_group")])
>
> (define_insn "cmpgtusi_t"
> [(set (reg:SI T_REG)
> (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
> (match_operand:SI 1 "arith_reg_operand" "r")))]
> ""
> ! "cmp/hi %1,%0"
> ! [(set_attr "insn_class" "mt_group")])
>
> ;; We save the compare operands in the cmpxx patterns and
> use them when
> ;; we generate the branch.
> ***************
> *** 841,847 ****
> (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
> ""
> "addc %2,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "addc1"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 869,876 ----
> (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
> ""
> "addc %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "addc1"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 851,857 ****
> (clobber (reg:SI T_REG))]
> ""
> "addc %2,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "addsi3"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 880,887 ----
> (clobber (reg:SI T_REG))]
> ""
> "addc %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "addsi3"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 859,866 ****
> (match_operand:SI 2 "arith_operand" "rI")))]
> ""
> "add %2,%0"
> ! [(set_attr "type" "arith")])
> !
>
> ;;
> --------------------------------------------------------------
> -----------
> ;; Subtraction instructions
> ;;
> --------------------------------------------------------------
> -----------
> --- 889,897 ----
> (match_operand:SI 2 "arith_operand" "rI")))]
> ""
> "add %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
> !
> ;;
> --------------------------------------------------------------
> -----------
> ;; Subtraction instructions
> ;;
> --------------------------------------------------------------
> -----------
> ***************
> *** 907,913 ****
> (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
> ""
> "subc %2,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "subc1"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 938,945 ----
> (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
> ""
> "subc %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "subc1"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 917,923 ****
> (clobber (reg:SI T_REG))]
> ""
> "subc %2,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "*subsi3_internal"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 949,956 ----
> (clobber (reg:SI T_REG))]
> ""
> "subc %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "*subsi3_internal"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 925,931 ****
> (match_operand:SI 2 "arith_reg_operand" "r")))]
> ""
> "sub %2,%0"
> ! [(set_attr "type" "arith")])
>
> ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
> ;; will sometimes save one instruction. Otherwise we might get
> --- 958,965 ----
> (match_operand:SI 2 "arith_reg_operand" "r")))]
> ""
> "sub %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
> ;; will sometimes save one instruction. Otherwise we might get
> ***************
> *** 1492,1498 ****
> (match_operand:SI 2 "logical_operand" "r,L")))]
> ""
> "and %2,%0"
> ! [(set_attr "type" "arith")])
>
> ;; If the constant is 255, then emit a extu.b instruction
> instead of an
> ;; and, since that will give better code.
> --- 1526,1533 ----
> (match_operand:SI 2 "logical_operand" "r,L")))]
> ""
> "and %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> ;; If the constant is 255, then emit a extu.b instruction
> instead of an
> ;; and, since that will give better code.
> ***************
> *** 1518,1524 ****
> (match_operand:SI 2 "logical_operand" "r,L")))]
> ""
> "or %2,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "xorsi3"
> [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
> --- 1553,1560 ----
> (match_operand:SI 2 "logical_operand" "r,L")))]
> ""
> "or %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "xorsi3"
> [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
> ***************
> *** 1526,1533 ****
> (match_operand:SI 2 "logical_operand" "L,r")))]
> ""
> "xor %2,%0"
> ! [(set_attr "type" "arith")])
> !
>
> ;;
> --------------------------------------------------------------
> -----------
> ;; Shifts and rotates
> ;;
> --------------------------------------------------------------
> -----------
> --- 1562,1570 ----
> (match_operand:SI 2 "logical_operand" "L,r")))]
> ""
> "xor %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
> !
> ;;
> --------------------------------------------------------------
> -----------
> ;; Shifts and rotates
> ;;
> --------------------------------------------------------------
> -----------
> ***************
> *** 1540,1546 ****
> (lshiftrt:SI (match_dup 1) (const_int 31)))]
> ""
> "rotl %0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "rotlsi3_31"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 1577,1584 ----
> (lshiftrt:SI (match_dup 1) (const_int 31)))]
> ""
> "rotl %0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "rotlsi3_31"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 1549,1555 ****
> (clobber (reg:SI T_REG))]
> ""
> "rotr %0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "rotlsi3_16"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 1587,1594 ----
> (clobber (reg:SI T_REG))]
> ""
> "rotr %0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "rotlsi3_16"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 1557,1563 ****
> (const_int 16)))]
> ""
> "swap.w %1,%0"
> ! [(set_attr "type" "arith")])
>
> (define_expand "rotlsi3"
> [(set (match_operand:SI 0 "arith_reg_operand" "")
> --- 1596,1603 ----
> (const_int 16)))]
> ""
> "swap.w %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_expand "rotlsi3"
> [(set (match_operand:SI 0 "arith_reg_operand" "")
> ***************
> *** 1621,1627 ****
> (const_int 8)))]
> ""
> "swap.b %1,%0"
> ! [(set_attr "type" "arith")])
>
> (define_expand "rotlhi3"
> [(set (match_operand:HI 0 "arith_reg_operand" "")
> --- 1661,1668 ----
> (const_int 8)))]
> ""
> "swap.b %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_expand "rotlhi3"
> [(set (match_operand:HI 0 "arith_reg_operand" "")
> ***************
> *** 1663,1669 ****
> (clobber (match_dup 4))])]
> "operands[4] = gen_rtx_SCRATCH (SImode);"
> [(set_attr "length" "*,*,*,4")
> ! (set_attr "type" "dyn_shift,arith,arith,arith")])
>
> (define_insn "ashlhi3_k"
> [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
> --- 1704,1711 ----
> (clobber (match_dup 4))])]
> "operands[4] = gen_rtx_SCRATCH (SImode);"
> [(set_attr "length" "*,*,*,4")
> ! (set_attr "type" "dyn_shift,arith,arith,arith")
> ! (set_attr "insn_class" "ex_group,ex_group,ex_group,ex_group")])
>
> (define_insn "ashlhi3_k"
> [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
> ***************
> *** 1673,1679 ****
> "@
> add %0,%0
> shll%O2 %0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "ashlsi3_n"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 1715,1722 ----
> "@
> add %0,%0
> shll%O2 %0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "ashlsi3_n"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 1690,1696 ****
> (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
> (const_string "6")]
> (const_string "8")))
> ! (set_attr "type" "arith")])
>
> (define_split
> [(set (match_operand:SI 0 "arith_reg_operand" "")
> --- 1733,1740 ----
> (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
> (const_string "6")]
> (const_string "8")))
> ! (set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_split
> [(set (match_operand:SI 0 "arith_reg_operand" "")
> ***************
> *** 1764,1770 ****
> (clobber (reg:SI T_REG))]
> "INTVAL (operands[2]) == 1"
> "shar %0"
> ! [(set_attr "type" "arith")])
>
> ;; We can't do HImode right shifts correctly unless we
> start out with an
> ;; explicit zero / sign extension; doing that would result in worse
> overall
> --- 1808,1815 ----
> (clobber (reg:SI T_REG))]
> "INTVAL (operands[2]) == 1"
> "shar %0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> ;; We can't do HImode right shifts correctly unless we
> start out with an
> ;; explicit zero / sign extension; doing that would result in worse
> overall
> ***************
> *** 1823,1829 ****
> (lt:SI (match_dup 1) (const_int 0)))]
> ""
> "shll %0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "ashrsi3_d"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 1868,1875 ----
> (lt:SI (match_dup 1) (const_int 0)))]
> ""
> "shll %0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "ashrsi3_d"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 1831,1837 ****
> (neg:SI (match_operand:SI 2 "arith_reg_operand"
> "r"))))]
> "TARGET_SH3"
> "shad %2,%0"
> ! [(set_attr "type" "dyn_shift")])
>
> (define_insn "ashrsi3_n"
> [(set (reg:SI R4_REG)
> --- 1877,1884 ----
> (neg:SI (match_operand:SI 2 "arith_reg_operand"
> "r"))))]
> "TARGET_SH3"
> "shad %2,%0"
> ! [(set_attr "type" "dyn_shift")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "ashrsi3_n"
> [(set (reg:SI R4_REG)
> ***************
> *** 1861,1867 ****
> (neg:SI (match_operand:SI 2 "arith_reg_operand"
> "r"))))]
> "TARGET_SH3"
> "shld %2,%0"
> ! [(set_attr "type" "dyn_shift")])
>
> ;; Only the single bit shift clobbers the T bit.
>
> --- 1908,1915 ----
> (neg:SI (match_operand:SI 2 "arith_reg_operand"
> "r"))))]
> "TARGET_SH3"
> "shld %2,%0"
> ! [(set_attr "type" "dyn_shift")
> ! (set_attr "insn_class" "ex_group")])
>
> ;; Only the single bit shift clobbers the T bit.
>
> ***************
> *** 1872,1878 ****
> (clobber (reg:SI T_REG))]
> "CONST_OK_FOR_M (INTVAL (operands[2]))"
> "shlr %0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "lshrsi3_k"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 1920,1927 ----
> (clobber (reg:SI T_REG))]
> "CONST_OK_FOR_M (INTVAL (operands[2]))"
> "shlr %0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "lshrsi3_k"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 1881,1887 ****
> "CONST_OK_FOR_K (INTVAL (operands[2]))
> && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
> "shlr%O2 %0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "lshrsi3_n"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 1930,1937 ----
> "CONST_OK_FOR_K (INTVAL (operands[2]))
> && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
> "shlr%O2 %0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "lshrsi3_n"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 1945,1951 ****
> ""
> "shll %R0\;rotcl %S0"
> [(set_attr "length" "4")
> ! (set_attr "type" "arith")])
>
> (define_expand "ashldi3"
> [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
> --- 1995,2002 ----
> ""
> "shll %R0\;rotcl %S0"
> [(set_attr "length" "4")
> ! (set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_expand "ashldi3"
> [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
> ***************
> *** 1966,1972 ****
> ""
> "shlr %S0\;rotcr %R0"
> [(set_attr "length" "4")
> ! (set_attr "type" "arith")])
>
> (define_expand "lshrdi3"
> [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
> --- 2017,2024 ----
> ""
> "shlr %S0\;rotcr %R0"
> [(set_attr "length" "4")
> ! (set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_expand "lshrdi3"
> [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
> ***************
> *** 1987,1993 ****
> ""
> "shar %S0\;rotcr %R0"
> [(set_attr "length" "4")
> ! (set_attr "type" "arith")])
>
> (define_expand "ashrdi3"
> [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
> --- 2039,2046 ----
> ""
> "shar %S0\;rotcr %R0"
> [(set_attr "length" "4")
> ! (set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_expand "ashrdi3"
> [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
> ***************
> *** 2203,2209 ****
> (const_int 16))))]
> ""
> "xtrct %1,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "xtrct_right"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> --- 2256,2263 ----
> (const_int 16))))]
> ""
> "xtrct %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "xtrct_right"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> ***************
> *** 2213,2220 ****
> (const_int 16))))]
> ""
> "xtrct %2,%0"
> ! [(set_attr "type" "arith")])
> !
>
> ;;
> --------------------------------------------------------------
> -----------
> ;; Unary arithmetic
> ;;
> --------------------------------------------------------------
> -----------
> --- 2267,2275 ----
> (const_int 16))))]
> ""
> "xtrct %2,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
> !
> ;;
> --------------------------------------------------------------
> -----------
> ;; Unary arithmetic
> ;;
> --------------------------------------------------------------
> -----------
> ***************
> *** 2228,2234 ****
> (const_int 0)))]
> ""
> "negc %1,%0"
> ! [(set_attr "type" "arith")])
>
> (define_expand "negdi2"
> [(set (match_operand:DI 0 "arith_reg_operand" "")
> --- 2283,2290 ----
> (const_int 0)))]
> ""
> "negc %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_expand "negdi2"
> [(set (match_operand:DI 0 "arith_reg_operand" "")
> ***************
> *** 2257,2271 ****
> (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
> ""
> "neg %1,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "one_cmplsi2"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
> ""
> "not %1,%0"
> ! [(set_attr "type" "arith")])
> !
>
> ;;
> --------------------------------------------------------------
> -----------
> ;; Zero extension instructions
> ;;
> --------------------------------------------------------------
> -----------
> --- 2313,2329 ----
> (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
> ""
> "neg %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "one_cmplsi2"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
> ""
> "not %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
> !
> ;;
> --------------------------------------------------------------
> -----------
> ;; Zero extension instructions
> ;;
> --------------------------------------------------------------
> -----------
> ***************
> *** 2275,2296 ****
> (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
> ""
> "extu.w %1,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "zero_extendqisi2"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
> ""
> "extu.b %1,%0"
> ! [(set_attr "type" "arith")])
>
> (define_insn "zero_extendqihi2"
> [(set (match_operand:HI 0 "arith_reg_operand" "=r")
> (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
> ""
> "extu.b %1,%0"
> ! [(set_attr "type" "arith")])
> !
>
> ;;
> --------------------------------------------------------------
> -----------
> ;; Sign extension instructions
> ;;
> --------------------------------------------------------------
> -----------
> --- 2333,2357 ----
> (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
> ""
> "extu.w %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "zero_extendqisi2"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r")
> (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
> ""
> "extu.b %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
>
> (define_insn "zero_extendqihi2"
> [(set (match_operand:HI 0 "arith_reg_operand" "=r")
> (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
> ""
> "extu.b %1,%0"
> ! [(set_attr "type" "arith")
> ! (set_attr "insn_class" "ex_group")])
> !
> ;;
> --------------------------------------------------------------
> -----------
> ;; Sign extension instructions
> ;;
> --------------------------------------------------------------
> -----------
> ***************
> *** 2308,2314 ****
> "@
> exts.w %1,%0
> mov.w %1,%0"
> ! [(set_attr "type" "arith,load")])
>
> (define_insn "extendqisi2"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
> --- 2369,2376 ----
> "@
> exts.w %1,%0
> mov.w %1,%0"
> ! [(set_attr "type" "arith,load")
> ! (set_attr "insn_class" "ex_group,*")])
>
> (define_insn "extendqisi2"
> [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
> ***************
> *** 2317,2323 ****
> "@
> exts.b %1,%0
> mov.b %1,%0"
> ! [(set_attr "type" "arith,load")])
>
> (define_insn "extendqihi2"
> [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
> --- 2379,2386 ----
> "@
> exts.b %1,%0
> mov.b %1,%0"
> ! [(set_attr "type" "arith,load")
> ! (set_attr "insn_class" "ex_group,*")])
>
> (define_insn "extendqihi2"
> [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
> ***************
> *** 2326,2333 ****
> "@
> exts.b %1,%0
> mov.b %1,%0"
> ! [(set_attr "type" "arith,load")])
> !
>
> ;;
> --------------------------------------------------------------
> -----------
> ;; Move instructions
> ;;
> --------------------------------------------------------------
> -----------
> --- 2389,2397 ----
> "@
> exts.b %1,%0
> mov.b %1,%0"
> ! [(set_attr "type" "arith,load")
> ! (set_attr "insn_class" "ex_group,*")])
> !
> ;;
> --------------------------------------------------------------
> -----------
> ;; Move instructions
> ;;
> --------------------------------------------------------------
> -----------
> ***************
> *** 2435,2440 ****
> --- 2499,2505 ----
> lds.l %1,%0
> fake %1,%0"
> [(set_attr "type"
> "pcload_si,move,*,load_si,move,prget,move,store,store,pstore,m
> ove,prset,load
> ,pload,pcload_si")
> + (set_attr "insn_class" "*,*,mt_group,*,*,*,*,*,*,*,*,*,*,*,*")
> (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
>
> ;; t/r must come after r/r, lest reload will try to reload
> stuff like
> ***************
> *** 2516,2522 ****
> (clobber (match_scratch:SI 2 "=&r"))]
> "TARGET_HARD_SH4"
> "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
> ! [(set_attr "length" "8")])
>
> (define_insn "movqi_i"
> [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
> --- 2581,2588 ----
> (clobber (match_scratch:SI 2 "=&r"))]
> "TARGET_HARD_SH4"
> "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
> ! [(set_attr "length" "8")
> ! (set_attr "insn_class" "cwb")])
>
> (define_insn "movqi_i"
> [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
> ***************
> *** 4405,4411 ****
> mov.l %1,%0
> sts fpscr,%0"
> [(set_attr "length" "0,2,2,4,2,2,2,2")
> ! (set_attr "type"
> "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
>
> (define_split
> [(set (reg:PSI FPSCR_REG)
> --- 4471,4478 ----
> mov.l %1,%0
> sts fpscr,%0"
> [(set_attr "length" "0,2,2,4,2,2,2,2")
> ! (set_attr "type"
> "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")
> ! (set_attr "insn_class"
> "ldsmem_to_fpscr,*,*,lds_to_fpscr,*,*,*,*")])
>
> (define_split
> [(set (reg:PSI FPSCR_REG)
> ***************
> *** 5207,5209 ****
> --- 5274,5566 ----
> ""
> "mov.l @r15+,r15\;mov.l @r15+,r0"
> [(set_attr "length" "4")])
> +
> + ;; The following description models the
> + ;; SH4 pipeline using the DFA based scheduler.
> + ;; The DFA based description is better way to model
> + ;; a superscalar pipeline as compared to function unit
> + ;; reservation model.
> + ;; 1. The function unit based model is oriented to describe
> at most one
> + ;; unit reservation by each insn. It is difficult to model unit
> reservations in multiple
> + ;; pipeline units by same insn. This can be done using DFA based
> description.
> + ;; 2. The execution performance of DFA based scheduler does
> not depend on
> processor complexity.
> + ;; 3. Writing all unit reservations for an instruction class is more
> natural description
> + ;; of the pipeline and makes interface of the hazard
> recognizer simpler
> than the
> + ;; old function unit based model.
> + ;; 4. The DFA model is richer and is a part of greater
> overall framework
> of RCSP.
> +
> +
> + ;; Two automata are defined to reduce number of states
> + ;; which a single large automaton will have.(Factoring)
> +
> + (define_automaton "inst_pipeline,fpu_pipe")
> +
> + ;; This unit is basically the decode unit of the processor.
> + ;; Since SH4 is a dual issue machine,it is as if there are two
> + ;; units so that any insn can be processed by either one
> + ;; of the decoding unit.
> +
> + (define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
> +
> +
> + ;; The fixed point arithmetic calculator(?? EX Unit).
> +
> + (define_cpu_unit "int" "inst_pipeline")
> +
> + ;; f1_1 and f1_2 are floating point units.Actually there is
> + ;; a f1 unit which can overlap with other f1 unit but
> + ;; not another F1 unit.It is as though there were two
> + ;; f1 units.
> +
> + (define_cpu_unit "f1_1,f1_2" "fpu_pipe")
> +
> + ;; The floating point units.
> +
> + (define_cpu_unit "F1,F2,F3,FS" "fpu_pipe")
> +
> + ;; This is basically the MA unit of SH4
> + ;; used in LOAD/STORE pipeline.
> +
> + (define_cpu_unit "memory" "inst_pipeline")
> +
> + ;; The address calculator used for branch instructions.
> + ;; This will be reserved with "issue" of branch instructions
> + ;; and this is to make sure that no two branch instructions
> + ;; can be issued in parallel.
> +
> + (define_cpu_unit "pcr_addrcalc" "inst_pipeline")
> +
> + ;; ----------------------------------------------------
> + ;; This reservation is to simplify the dual issue description.
> +
> + (define_reservation "issue" "pipe_01|pipe_02")
> +
> + ;; This is to express the locking of D stage.
> +
> + (define_reservation "d_lock" "pipe_01+pipe_02")
> +
> + ;; This is to simplify description where F1,F2,FS
> + ;; are used simultaneously.
> +
> + (define_reservation "fpu" "F1+F2+FS")
> +
> + ;; This is to highlight the fact that f1
> + ;; cannot overlap with F1.
> +
> + (exclusion_set "f1_1,f1_2" "F1")
> +
> + ;; Although reg moves have a latency of zero
> + ;; we need to highlight that they use D stage
> + ;; for one cycle.
> +
> + (define_insn_reservation "reg_mov" 0
> + (eq_attr "type" "move,fmove")
> + "issue")
> +
> + ;; Other MT group intructions(1 step operations)
> + ;; Group: MT
> + ;; Latency: 1
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "mt" 1
> + (eq_attr "insn_class" "mt_group")
> + "issue,nothing")
> +
> + ;; Fixed Point Arithmetic Instructions(1 step operations)
> + ;; Group: EX
> + ;; Latency: 1
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "simple_arith" 1
> + (eq_attr "insn_class" "ex_group")
> + "issue,int")
> +
> + ;; Load Store instructions. (MOV.[BWL]@(d,GBR)
> + ;; Group: LS
> + ;; Latency: 2
> + ;; Issue Rate: 1
> + ;; Uses "int" for address calculation.
> +
> + (define_insn_reservation "load_store" 2
> + (eq_attr "type" "load,load_si,store")
> + "issue,memory*2")
> +
> + ;; Branch (BF,BF/S,BT,BT/S,BRA)
> + ;; Group: BR
> + ;; Latency: 2 (or 1) Actually Observed to be 5/7
> + ;; Issue Rate: 1
> + ;; The latency is 1 when displacement is 0.
> + ;; This reservation can be further broken into 2
> + ;; 1. branch_zero : One with latency 1 and in the TEST
> + ;; part it also checks for 0 (ZERO) displacement
> + ;; 2. branch: Latency 2.
> +
> + (define_insn_reservation "branch_zero" 5
> + (and (eq_attr "type" "cbranch")
> + (eq_attr "length" "2"))
> + "(issue+pcr_addrcalc),pcr_addrcalc,nothing")
> +
> + (define_insn_reservation "branch" 7
> + (eq_attr "type" "cbranch")
> + "(issue+pcr_addrcalc),pcr_addrcalc,nothing")
> +
> + ;; Branch Far (JMP,RTS,BRAF)
> + ;; Group: CO
> + ;; Latency: 3
> + ;; Issue Rate: 2
> + ;; Since issue stage (D stage) is blocked for 2nd cycle,
> + ;; cpu_unit int is reserved since it might be required for far
> + ;; address calculation.
> +
> + (define_insn_reservation "branch_far" 12
> + (and (eq_attr "type" "jump,return")
> + (eq_attr "length" "6"))
> + "d_lock*2,int+pcr_addrcalc,pcr_addrcalc")
> +
> + ;; RTE
> + ;; Group: CO
> + ;; atency: 5
> + ;; ssue Rate: 5
> + ;; this instruction can be executed in any of the pipelines
> + ;; and blocks the pipeline for next 4 stages.
> +
> + (define_insn_reservation "return_from_exp" 5
> + (eq_attr "type" "rte")
> + "(issue+pcr_addrcalc),d_lock*4,int+pcr_addrcalc,nothing")
> +
> + ;; OCBP, OCBWB
> + ;; Group: CO
> + ;; Latency: 5
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "ocbwb" 5
> + (eq_attr "insn_class" "cwb")
> + "issue,(int+memory),memory*5")
> +
> + ;; LDS to PR,JSR
> + ;; Group: CO
> + ;; Latency: 3
> + ;; Issue Rate: 2
> + ;; The SX stage is blocked for last 2 cycles.
> +
> + (define_insn_reservation "lds_to_pr" 3
> + (eq_attr "type" "prset,call,sfunc")
> +
> "(issue+pcr_addrcalc),(issue+int+pcr_addrcalc),(int+pcr_addrcalc)*2")
> +
> + ;; LDS.L to PR
> + ;; Group: CO
> + ;; Latency: 3
> + ;; Issue Rate: 2
> + ;; The SX unit is blocked for last 2 cycles.
> +
> + (define_insn_reservation "ldsmem_to_pr" 3
> + (eq_attr "type" "pload")
> +
> "(issue+pcr_addrcalc),(issue+int+pcr_addrcalc),(int+memory+pcr
> _addrcalc),(in
> t+pcr_addrcalc)")
> +
> + ;; STS from PR
> + ;; Group: CO
> + ;; Latency: 2
> + ;; Issue Rate: 2
> + ;; The SX unit in second and third cycles.
> +
> + (define_insn_reservation "sts_from_pr" 2
> + (eq_attr "type" "prget")
> +
> "(issue+pcr_addrcalc),(pipe_01+int+pcr_addrcalc),(int+pcr_addr
> calc),nothing"
> )
> +
> + ;; STS.L from PR
> + ;; Group: CO
> + ;; Latency: 2
> + ;; Issue Rate: 2
> +
> + (define_insn_reservation "prload_mem" 2
> + (eq_attr "type" "pstore")
> +
> "(issue+pcr_addrcalc),(pipe_01+int+pcr_addrcalc),(int+memory+p
> cr_addrcalc),m
> emory")
> +
> + ;; LDS to FPSCR
> + ;; Group: CO
> + ;; Latency: 4
> + ;; Issue Rate: 1
> + ;; F1 is blocked for last three cycles.
> +
> + (define_insn_reservation "fpscr_store" 4
> + (eq_attr "insn_class" "lds_to_fpscr")
> + "issue,int,F1*3")
> +
> + ;; LDS.L to FPSCR
> + ;; Group: CO
> + ;; Latency: 1 / 4
> + ;; Latency to update Rn is 1 and latency to update FPSCR is 4
> + ;; Issue Rate: 1
> + ;; F1 is blocked for last three cycles.
> +
> + (define_insn_reservation "fpscr_store_mem" 4
> + (eq_attr "insn_class" "ldsmem_to_fpscr")
> + "issue,(int+memory),(F1+memory),F1*2")
> +
> +
>
> + ;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
> + ;; Group: CO
> + ;; Latency: 4 / 4
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "multi" 4
> + (eq_attr "type" "smpy,dmpy")
> + "issue,(issue+int+f1_1),(int+f1_1),(f1_1|f1_2)*2,F2,FS")
> +
> +
> + ;; Single precision floating point computation FCMP/EQ,
> + ;; FCP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG
> + ;; Group: FE
> + ;; Latency: 4
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "fp_arith" 4
> + (eq_attr "type" "fp")
> + "issue,F1,F2,FS")
> +
> + ;; Single Precision FDIV/SQRT
> + ;; Group: FE
> + ;; Latency: 12/13
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "fp_div" 13
> + (eq_attr "type" "fdiv")
> + "issue,F1+F3,F1+F2+F3,F3*7,F1+F3,F2,FS")
> +
> + ;; Double Precision floating point computation
> + ;; (FCNVDS, FCNVSD, FLOAT, FTRC)
> + ;; Group: FE
> + ;; Latency: (3,4)/5
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "dp_float" 5
> + (eq_attr "type" "dfp_conv")
> + "issue,F1,F1+F2,F2+FS,FS")
> +
> + ;; Double-precision floating-point (FADD ,FMUL,FSUB)
> + ;; Group: FE
> + ;; Latency: (7,8)/9
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "fp_double_arith" 9
> + (eq_attr "type" "dfp_arith")
> + "issue,F1,F1+F2,fpu*4,F2+FS,FS")
> +
> + ;; Double-precision FCMP (FCMP/EQ,FCMP/GT)
> + ;; Group: FE
> + ;; Latency: 3/5
> + ;; Issue Rate: 2
> +
> + (define_insn_reservation "fp_double_cmp" 5
> + (eq_attr "type" "dfp_cmp")
> + "issue,(issue+F1),F1+F2,F2+FS,FS")
> +
> + ;; Double precision FDIV/SQRT
> + ;; Group: FE
> + ;; Latency: (24,25)/26
> + ;; Issue Rate: 1
> +
> + (define_insn_reservation "dp_div" 26
> + (eq_attr "type" "dfdiv")
> +
> "issue,F1+F3,F1+F2+F3,F2+F3+FS,F3*16,F1+F3,F1+F2+F3,fpu+F3,F2+FS,FS")
> +
>
>
Attachment:
Summary.txt
Description: Text document
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