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PATCH: minor rs6000 specific
- From: Dale Johannesen <dalej at apple dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 12 Dec 2001 10:33:12 -0800
- Subject: PATCH: minor rs6000 specific
Bootstrapped and tested on Darwin.
2001-12-12 Dale Johannesen <dalej@apple.com>
* config/rs6000/rs6000.h: CPP_CPU_SPEC: add mcpu=7400.
ASM_CPU_SPEC: Ditto.
RTX_COSTS: Fix timing info for 7450 multiply.
config/rs6000/rs6000.md: Fix timing info for 7450 imul.
Allow floats to be kept in int regs in movsf_low,
movsf_low_st (Darwin only)
Index: rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.154
diff -u -d -b -w -c -3 -p -r1.154 rs6000.h
cvs server: conflicting specifications of output style
*** rs6000.h 2001/12/07 03:03:43 1.154
--- rs6000.h 2001/12/12 18:22:45
*************** Boston, MA 02111-1307, USA. */
*** 76,81 ****
--- 76,82 ----
%{mcpu=604e: -D_ARCH_PPC} \
%{mcpu=620: -D_ARCH_PPC} \
%{mcpu=740: -D_ARCH_PPC} \
+ %{mcpu=7400: -D_ARCH_PPC} \
%{mcpu=7450: -D_ARCH_PPC} \
%{mcpu=750: -D_ARCH_PPC} \
%{mcpu=801: -D_ARCH_PPC} \
*************** Boston, MA 02111-1307, USA. */
*** 114,119 ****
--- 115,121 ----
%{mcpu=604e: -mppc} \
%{mcpu=620: -mppc} \
%{mcpu=740: -mppc} \
+ %{mcpu=7400: -mppc} \
%{mcpu=7450: -mppc} \
%{mcpu=750: -mppc} \
%{mcpu=801: -mppc} \
*************** do {
\
*** 2324,2335 ****
return COSTS_N_INSNS (5); \
case PROCESSOR_PPC603: \
case PROCESSOR_PPC7400: \
- case PROCESSOR_PPC7450: \
case PROCESSOR_PPC750: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? COSTS_N_INSNS (5) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <=
255 \
? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
case PROCESSOR_PPC403: \
case PROCESSOR_PPC604: \
return COSTS_N_INSNS (4); \
--- 2344,2358 ----
return COSTS_N_INSNS (5); \
case PROCESSOR_PPC603: \
case PROCESSOR_PPC7400: \
case PROCESSOR_PPC750: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? COSTS_N_INSNS (5) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <=
255 \
? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
+ case PROCESSOR_PPC7450: \
+ return (GET_CODE (XEXP (X, 1)) != CONST_INT \
+ ? COSTS_N_INSNS (4) \
+ : COSTS_N_INSNS (3)); \
case PROCESSOR_PPC403: \
case PROCESSOR_PPC604: \
return COSTS_N_INSNS (4); \
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.143
diff -u -d -b -w -c -3 -p -r1.143 rs6000.md
cvs server: conflicting specifications of output style
*** rs6000.md 2001/12/07 22:17:02 1.143
--- rs6000.md 2001/12/12 18:23:53
***************
*** 309,315 ****
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc7450"))
! 4 4)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul2,imul3")
--- 309,315 ----
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc7450"))
! 4 2)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul2,imul3")
***************
*** 7558,7577 ****
(set_attr "length" "4")])
(define_insn "movsf_low"
! [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
! "lfs %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn "movsf_low_st"
! [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
(match_operand 2 "" "")))
! (match_operand:SF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
! "stfs %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
--- 7558,7581 ----
(set_attr "length" "4")])
(define_insn "movsf_low"
! [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
! (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
! "@
! lfs %0,lo16(%2)(%1)
! {l|lwz} %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn "movsf_low_st"
! [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b")
(match_operand 2 "" "")))
! (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
! "@
! stfs %0,lo16(%2)(%1)
! {st|stw} %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])