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Re: sh-unknown-linux-gnu (Support of no fdiv for integer division)
I said:
> I'd say, I like '-mno-implicit-fp' as William C. Cox suggested.
And the change. I think that this change is better than implementing
-m4-no-fpu.
2001-10-12 NIIBE Yutaka <gniibe@m17n.org>
* config/sh/sh.md (udivsi3_i1, udivsi3, divsi3_i1, divsi3):
Handle the case of TARGET_NO_IMPLICIT_FP.
* config/sh/sh.h (NO_IMPLICIT_FP_BIT): New flag.
(TARGET_NO_IMPLICIT_FP): Added.
(TARGET_SWITCHES): Add no-implicit-fp switch.
* doc/invoke.texi (SH Options): Add descriopton of -mno-implicit-fp.
Index: gcc/config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.117
diff -c -3 -p -r1.117 sh.h
*** gcc/config/sh/sh.h 2001/09/21 00:53:28 1.117
--- gcc/config/sh/sh.h 2001/10/12 09:03:37
*************** extern int target_flags;
*** 134,139 ****
--- 134,140 ----
#define HARD_SH4_BIT (1<<5)
#define FPU_SINGLE_BIT (1<<7)
#define SH4_BIT (1<<12)
+ #define NO_IMPLICIT_FP_BIT (1<<3)
#define FMOVD_BIT (1<<4)
#define SPACE_BIT (1<<13)
#define BIGTABLE_BIT (1<<14)
*************** extern int target_flags;
*** 182,187 ****
--- 183,191 ----
/* Nonzero if we should generate code using type 4 insns. */
#define TARGET_SH4 (target_flags & SH4_BIT)
+ /* Nonzero if we should not use FPU implicitly. */
+ #define TARGET_NO_IMPLICIT_FP (target_flags & NO_IMPLICIT_FP_BIT)
+
/* Nonzero if we should generate fmovd. */
#define TARGET_FMOVD (target_flags & FMOVD_BIT)
*************** extern int target_flags;
*** 251,256 ****
--- 255,261 ----
{"isize", ISIZE_BIT, "" }, \
{"l", LITTLE_ENDIAN_BIT, "" }, \
{"no-ieee", -IEEE_BIT, "" }, \
+ {"no-implicit-fp", NO_IMPLICIT_FP_BIT, "" }, \
{"padstruct", PADSTRUCT_BIT, "" }, \
{"prefergot", PREFERGOT_BIT, "" }, \
{"relax", RELAX_BIT, "" }, \
Index: gcc/config/sh/sh.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.md,v
retrieving revision 1.89
diff -c -3 -p -r1.89 sh.md
*** gcc/config/sh/sh.md 2001/08/18 00:53:20 1.89
--- gcc/config/sh/sh.md 2001/10/12 09:03:37
***************
*** 981,987 ****
(clobber (reg:SI PR_REG))
(clobber (reg:SI R4_REG))
(use (match_operand:SI 1 "arith_reg_operand" "r"))]
! "! TARGET_SH4"
"jsr @%1%#"
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
--- 981,987 ----
(clobber (reg:SI PR_REG))
(clobber (reg:SI R4_REG))
(use (match_operand:SI 1 "arith_reg_operand" "r"))]
! "! TARGET_SH4 || TARGET_NO_IMPLICIT_FP"
"jsr @%1%#"
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
***************
*** 1042,1048 ****
operands[3] = gen_reg_rtx(SImode);
/* Emit the move of the address to a pseudo outside of the libcall. */
! if (TARGET_HARD_SH4 && TARGET_SH3E)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
--- 1042,1048 ----
operands[3] = gen_reg_rtx(SImode);
/* Emit the move of the address to a pseudo outside of the libcall. */
! if (TARGET_HARD_SH4 && TARGET_SH3E && !TARGET_NO_IMPLICIT_FP)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
***************
*** 1076,1082 ****
(clobber (reg:SI R2_REG))
(clobber (reg:SI R3_REG))
(use (match_operand:SI 1 "arith_reg_operand" "r"))]
! "! TARGET_SH4"
"jsr @%1%#"
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
--- 1076,1082 ----
(clobber (reg:SI R2_REG))
(clobber (reg:SI R3_REG))
(use (match_operand:SI 1 "arith_reg_operand" "r"))]
! "! TARGET_SH4 || TARGET_NO_IMPLICIT_FP"
"jsr @%1%#"
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
***************
*** 1128,1134 ****
operands[3] = gen_reg_rtx(SImode);
/* Emit the move of the address to a pseudo outside of the libcall. */
! if (TARGET_HARD_SH4 && TARGET_SH3E)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
--- 1128,1134 ----
operands[3] = gen_reg_rtx(SImode);
/* Emit the move of the address to a pseudo outside of the libcall. */
! if (TARGET_HARD_SH4 && TARGET_SH3E && !TARGET_NO_IMPLICIT_FP)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
Index: gcc/doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.61
diff -c -3 -p -r1.61 invoke.texi
*** gcc/doc/invoke.texi 2001/10/11 17:02:35 1.61
--- gcc/doc/invoke.texi 2001/10/12 09:03:37
*************** Enable the use of the instruction @code{
*** 8664,8669 ****
--- 8664,8673 ----
@opindex mhitachi
Comply with the calling conventions defined by Hitachi.
+ @item -mno-implicit-fp
+ @opindex mno-implicit-fp
+ Disable the use of FPU implicitly (never use FPU for integer division).
+
@item -mnomacsave
@opindex mnomacsave
Mark the @code{MAC} register as call-clobbered, even if
--