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sh-unknown-linux-gnu (Support of no fdiv for integer division)
- To: gcc-patches at gcc dot gnu dot org
- Subject: sh-unknown-linux-gnu (Support of no fdiv for integer division)
- From: NIIBE Yutaka <gniibe at m17n dot org>
- Date: Mon, 1 Oct 2001 19:00:16 +0900 (JST)
- Cc: kaz Kojima <kkojima at rr dot iij4u dot or dot jp>
Hi there,
For SH-4, integer division uses FPU. For SH-4 kernel, we don't want
use FPU for division to support lazy FPU switching.
Something like following is needed to disable FPU use for integer
division.
The patch is against mainline CVS, which could be applied to 3.0
branch too.
2001-10-01 NIIBE Yutaka <gniibe@m17n.org>
* config/sh/sh.md (udivsi3_i1, udivsi3, divsi3_i1, divsi3):
Handle the case of TARGET_NO_FDIV_DIVSI.
* config/sh/sh.h (NO_FDIV_DIVSI_BIT): New flag.
(TARGET_NO_FDIV_DIVSI): Added.
(TARGET_SWITCHES): Add no-fdiv-divsi switch.
* doc/invoke.texi (SH Options): Add descriopton of -mno-fdiv-divsi.
Index: gcc/config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.117
diff -u -r1.117 sh.h
--- sh.h 2001/09/21 00:53:28 1.117
+++ sh.h 2001/10/01 09:30:25
@@ -134,6 +134,7 @@
#define HARD_SH4_BIT (1<<5)
#define FPU_SINGLE_BIT (1<<7)
#define SH4_BIT (1<<12)
+#define NO_FDIV_DIVSI_BIT (1<<3)
#define FMOVD_BIT (1<<4)
#define SPACE_BIT (1<<13)
#define BIGTABLE_BIT (1<<14)
@@ -182,6 +183,9 @@
/* Nonzero if we should generate code using type 4 insns. */
#define TARGET_SH4 (target_flags & SH4_BIT)
+/* Nonzero if we should not generate fdiv for integer division. */
+#define TARGET_NO_FDIV_DIVSI (target_flags & NO_FDIV_DIVSI_BIT)
+
/* Nonzero if we should generate fmovd. */
#define TARGET_FMOVD (target_flags & FMOVD_BIT)
@@ -251,6 +255,7 @@
{"isize", ISIZE_BIT, "" }, \
{"l", LITTLE_ENDIAN_BIT, "" }, \
{"no-ieee", -IEEE_BIT, "" }, \
+ {"no-fdiv-divsi", NO_FDIV_DIVSI_BIT, "" }, \
{"padstruct", PADSTRUCT_BIT, "" }, \
{"prefergot", PREFERGOT_BIT, "" }, \
{"relax", RELAX_BIT, "" }, \
Index: gcc/config/sh/sh.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.md,v
retrieving revision 1.89
diff -u -r1.89 sh.md
--- sh.md 2001/08/18 00:53:20 1.89
+++ sh.md 2001/10/01 09:30:26
@@ -981,7 +981,7 @@
(clobber (reg:SI PR_REG))
(clobber (reg:SI R4_REG))
(use (match_operand:SI 1 "arith_reg_operand" "r"))]
- "! TARGET_SH4"
+ "! TARGET_SH4 || TARGET_NO_FDIV_DIVSI"
"jsr @%1%#"
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
@@ -1042,7 +1042,7 @@
operands[3] = gen_reg_rtx(SImode);
/* Emit the move of the address to a pseudo outside of the libcall. */
- if (TARGET_HARD_SH4 && TARGET_SH3E)
+ if (TARGET_HARD_SH4 && TARGET_SH3E && !TARGET_NO_FDIV_DIVSI)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
@@ -1076,7 +1076,7 @@
(clobber (reg:SI R2_REG))
(clobber (reg:SI R3_REG))
(use (match_operand:SI 1 "arith_reg_operand" "r"))]
- "! TARGET_SH4"
+ "! TARGET_SH4 || TARGET_NO_FDIV_DIVSI"
"jsr @%1%#"
[(set_attr "type" "sfunc")
(set_attr "needs_delay_slot" "yes")])
@@ -1128,7 +1128,7 @@
operands[3] = gen_reg_rtx(SImode);
/* Emit the move of the address to a pseudo outside of the libcall. */
- if (TARGET_HARD_SH4 && TARGET_SH3E)
+ if (TARGET_HARD_SH4 && TARGET_SH3E && !TARGET_NO_FDIV_DIVSI)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
Index: gcc/doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.56
diff -u -r1.56 invoke.texi
--- invoke.texi 2001/09/29 16:33:20 1.56
+++ invoke.texi 2001/10/01 09:30:27
@@ -8624,6 +8624,10 @@
@opindex mhitachi
Comply with the calling conventions defined by Hitachi.
+@item -mno-fdiv-divsi
+@opindex mno-fdiv-divsi
+Disable the use of @code{fdiv} (Division with FPU) for integer division.
+
@item -mnomacsave
@opindex mnomacsave
Mark the @code{MAC} register as call-clobbered, even if
--