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Re: A bit of vector extension documentation

To: "Tim Prince" <tprince at computer dot org>
Subject: Re: A bit of vector extension documentation
From: Aldy Hernandez <aldyh at redhat dot com>
Date: 29 Sep 2001 17:32:15 -0400
Cc: "Toon Moene" <toon at moene dot indiv dot nluug dot nl>, "Diego Novillo" <dnovillo at redhat dot com>, "David Edelsohn" <dje at watson dot ibm dot com>, "Richard Henderson" <rth at redhat dot com>, "Daniel Berlin" <dan at cgsoftware dot com>, "Daniel Egger" <degger at fhm dot edu>, <gcc-patches at gcc dot gnu dot org>, <gcc at gcc dot gnu dot org>
References: <rth@redhat.com> <200109281712.NAA23750@makai.watson.ibm.com><20010928132532.A10203@tornado.cygnus.com><3BB4CB8E.DF6B40F4@moene.indiv.nluug.nl><014801c1485b$040450a0$7edd18ac@amr.corp.intel.com>

>>>>> "Tim" == Tim Prince <tprince@computer.org> writes:

 > To make it pay off on the Intel SIMD architectures, the compiler
 > must be able to analyze alignments, allocate arrays on 16-byte
 > boundaries, and pre-condition loops so that a majority of

same thing for altivec stuff.  It all needs to be 16 byte aligned.

Aldy

References:
- Re: A bit of vector extension documentation
  - From: David Edelsohn
- Re: A bit of vector extension documentation
  - From: Diego Novillo
- Re: A bit of vector extension documentation
  - From: Toon Moene
- Re: A bit of vector extension documentation
  - From: Tim Prince

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