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Re: SH4 ic_cache_invalidate code broken
- To: Alexandre Oliva <aoliva at redhat dot com>
- Subject: Re: SH4 ic_cache_invalidate code broken
- From: tm <tm at kloo dot net>
- Date: Fri, 27 Jul 2001 09:03:57 -0700
- Cc: Toshi Morita <tm2 at best dot com>, gcc-patches at gcc dot gnu dot org
- References: <200106042011.NAA20055@shell14.ba.best.com> <oru1zyiv50.fsf@guarana.lsd.ic.unicamp.br>
Alexandre Oliva wrote:
>
> On Jun 4, 2001, Toshi Morita <tm2@best.com> wrote:
>
> > I just thought of another failure mode for this code chunk.
> > It assumes that both ic_invalidate and the target thunk are
> > in the cacheable area.
>
> > If ic_invalidate is in the noncacheable area, then it will NOT
> > clear any cache lines.
>
> > I think, at the very minimum, these assumptions need to be
> > documented in comments so people will be less likely to trip
> > over them.
>
> Indeed. Will you please post a patch to that effect.
Okay, will try to do sometime this weekend.
>
> > It'd be nice if we could also generate a real hardware
> > cache clear (set ICI of the CCR) depending on if a define
> > is set, maybe something like HARDWARE_CACHE_CLEAR.
> > That way, the user can choose whether to use a fast
> > software line clear or a slow invalidate of the entire
> > instruction cache.
>
> I think you misunderstand the behavior of the current cache
> invalidate. It doesn't invalidate the entire instruction cache. It
> just picks a chunk of memory that uses the same cache line as the
> selected address, so that only that line is invalidated.
I believe I fully understand what it does. It jumps into the middle of a
huge chunk of code to flush out the specific icache line which needs
to be flushed.
That's why I said "whether to use a fast software LINE clear or a slow
invalidate of the entire instruction cache".
Toshi