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MIPS patch for reload_outcc pattern



The MIPS reload_outcc pattern uses two floating-point temporaries, claimed
with a TFmode scratch operand.  The current code asumes that the number
of the second register is one plus the first, which isn't true in 32-bit
mode.

Test case attached, will commit in gcc-c.torture/compile if approved.  An
executable test isn't needed since the assembler picks up the error.  Tested
for regressions on mips1/o32, mips4/o32 and mips4/eabi.  OK to apply?

2001-07-27  Richard Sandiford  <rsandifo@redhat.com>

	* config/mips/mips.md (reload_outcc): Use gen_simplify_subreg to
	access the two halves of the TFmode scratch operand.

Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.102
diff -u -p -d -r1.102 mips.md
--- mips.md	2001/07/20 10:35:33	1.102
+++ mips.md	2001/07/27 09:14:37
@@ -5685,8 +5685,11 @@ move\\t%0,%z4\\n\\
   else
     source = operands[1];
 
-  fp1 = gen_rtx_REG (SFmode, REGNO (operands[2]));
-  fp2 = gen_rtx_REG (SFmode, REGNO (operands[2]) + 1);
+  /* FP1 and FP2 are the two halves of the TFmode scratch operand.  They
+     will be single registers in 64-bit mode and register pairs in 32-bit mode.
+     SOURCE is loaded into FP1 and zero is loaded into FP2.  */
+  fp1 = simplify_subreg (SFmode, operands[2], TFmode, 0);
+  fp2 = simplify_subreg (SFmode, operands[2], TFmode, GET_MODE_SIZE (DFmode));
 
   emit_insn (gen_move_insn (fp1, source));
   emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0)));

Testcase:

void test (double a, double b)
{
  if (a != b)
    call (1);
  call (2);
  if (a != b)
    call (3);
}


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