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Re: IA64 HP-UX ILP32 mode patch
- To: Steve Ellcey <sje at cup dot hp dot com>
- Subject: Re: IA64 HP-UX ILP32 mode patch
- From: Richard Henderson <rth at redhat dot com>
- Date: Wed, 18 Jul 2001 16:04:28 -0700
- Cc: gcc-patches at gcc dot gnu dot org
- References: <200107182243.PAA20606@hpsje.cup.hp.com>
On Wed, Jul 18, 2001 at 03:43:11PM -0700, Steve Ellcey wrote:
> If we switched the inputs to addp4 (r14 and r15) around then it
> would work because r15 is a valid 32 bit address and all is well.
Oh, I hadn't realized that ia64 copied the asymmetric nonsense
from parisc too. Well, the solution is to copy the same sort
of solution -- see pa.c basereg_operand, in particular,
return (GET_CODE (op) == REG
&& REG_POINTER (op)
&& register_operand (op, mode));
Now, this will require you to create two patterns:
(define_insn "*ptr_extend_plus_1"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(unspec:DI
[(plus:SI (match_operand:SI 1 "basereg_operand" "r")
(match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
24))]
""
"addp4 %0 = %2, %1"
[(set_attr "itanium_class" "ialu")])
(define_insn "*ptr_extend_plus_2"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(unspec:DI
[(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
(match_operand:SI 2 "basereg_operand" "r"))]
24))]
""
"addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")])
r~