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Re: reload_in/out register class constraints


On Wed, Jul 18, 2001 at 11:01:42AM -0700, Mark Mitchell wrote:
> This needs documentation in some .texi file, probably, since it would
> seem to be something you need to know to make a new port.

It appears that none of the special cases wrt these patterns
were documented.


r~



Index: md.texi
===================================================================
RCS file: /cvs/gcc/egcs/gcc/doc/md.texi,v
retrieving revision 1.12
diff -c -p -d -r1.12 md.texi
*** md.texi	2001/07/09 06:10:09	1.12
--- md.texi	2001/07/18 21:32:47
*************** move between operand 0 and operand 1.  O
*** 2076,2081 ****
--- 2076,2092 ----
  register.  See the discussion of the @code{SECONDARY_RELOAD_CLASS}
  macro in @pxref{Register Classes}.
  
+ There are special restrictions on the form of the @code{match_operand}s
+ used in these patterns.  First, only the predicate for the reload 
+ operand is examined, i.e. @code{reload_in} examines operand 1, but not
+ the predicates for operand 0 or 2.  Second, there may only be one
+ alternative in the constraints.  Third, only a single register class
+ letter may be used for the constraint; subsequent constraint letters
+ are ignored.  As a special exception, an empty constraint string
+ matches the @code{ALL_REGS} register class.  This may relieve ports
+ of the burden of defining an @code{ALL_REGS} constraint letter just
+ for these patterns.
+ 
  @cindex @code{movstrict@var{m}} instruction pattern
  @item @samp{movstrict@var{m}}
  Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}


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