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PATCH: gcc/config/mips/mips.h reorg
- To: gcc-patches at gcc dot gnu dot org
- Subject: PATCH: gcc/config/mips/mips.h reorg
- From: Eric Christopher <echristo at twigboy dot cygnus dot com>
- Date: Thu, 21 Jun 2001 19:53:21 -0700 (PDT)
Here's a slight reorg of mips.h that will make the way for some port
contributions and just general cleanup of the port. This also deprecates
the use of -m<processor> for codegen and uses a specs modification to
allow backwards compatibility.
Tested on target=mips-elf and mips-tx39-elf.
Thoughts? Ok for mainline?
-eric
2001-06-21 Eric Christopher <echristo@redhat.com>
* config/mips/mips.h (MASK_MIPS3900): Remove.
(MASK_MIPS16,MASK_NO_CHECK_ZERO_DIV,MASK_CHECK_RANGE_DIV,
MASK_UNINIT_CONST_IN_RODATA): Change for 3900 mask removal.
(TARGET_MIPS3900): Change to use mips_cpu.
(TARGET_SWITCHES): Change 3900 and 4650 options to NULL.
(SUBTARGET_TARGET_OPTIONS): Add -march=, currently identical to
-mcpu=. Change help text for -mipsX.
(GENERATE_BRANCHLIKELY): Move TARGET_MIPS3900.
(ISA_HAS_BRANCHLIKELY): To here.
(CC1_CPU_SPEC): New.
(CC1_SPEC): Use here. Remove 4650 and 3900 options.
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.113
diff -u -p -w -r1.113 mips.h
--- mips.h 2001/06/08 11:52:56 1.113
+++ mips.h 2001/06/22 01:14:24
@@ -212,14 +212,13 @@ extern void sbss_section PARAMS ((void)
#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
-#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
-#define MASK_MIPS16 0x00200000 /* Generate mips16 code */
+#define MASK_MIPS16 0x00100000 /* Generate mips16 code */
#define MASK_NO_CHECK_ZERO_DIV \
- 0x00400000 /* divide by zero checking */
+ 0x00200000 /* divide by zero checking */
#define MASK_CHECK_RANGE_DIV \
- 0x00800000 /* divide result range checking */
+ 0x00400000 /* divide result range checking */
#define MASK_UNINIT_CONST_IN_RODATA \
- 0x01000000 /* Store uninitialized
+ 0x00800000 /* Store uninitialized
consts in rodata */
/* Debug switches, not documented */
@@ -246,9 +245,6 @@ extern void sbss_section PARAMS ((void)
/* Mips vs. GNU linker */
#define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
-/* generate mips 3900 insns */
-#define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
-
/* Mips vs. GNU assembler */
#define TARGET_GAS (target_flags & MASK_GAS)
#define TARGET_MIPS_AS (!TARGET_GAS)
@@ -330,6 +326,9 @@ extern void sbss_section PARAMS ((void)
/* Generate mips16 code */
#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
+/* CPU specific target defines. */
+#define TARGET_MIPS3900 (mips_cpu == PROCESSOR_R3900)
+
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
@@ -430,10 +429,10 @@ extern void sbss_section PARAMS ((void)
N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
N_("Don't work around early 4300 hardware bug")}, \
- {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
- N_("Optimize for 4650")}, \
- {"3900", MASK_MIPS3900, \
+ {"3900", 0, \
N_("Optimize for 3900")}, \
+ {"4650", 0, \
+ N_("Optimize for 4650")}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
N_("Trap on integer divide by zero")}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
@@ -567,8 +566,10 @@ extern void sbss_section PARAMS ((void)
SUBTARGET_TARGET_OPTIONS \
{ "cpu=", &mips_cpu_string, \
N_("Specify CPU for scheduling purposes")}, \
+ { "arch=", &mips_cpu_string, \
+ N_("Specify CPU for code generation purposes")}, \
{ "ips", &mips_isa_string, \
- N_("Specify MIPS ISA")}, \
+ N_("Specify a Standard MIPS ISA")}, \
{ "entry", &mips_entry_string, \
N_("Use mips16 entry/exit psuedo ops")}, \
{ "no-mips16", &mips_no_mips16_string, \
@@ -580,7 +581,7 @@ extern void sbss_section PARAMS ((void)
/* This is meant to be redefined in the host dependent files. */
#define SUBTARGET_TARGET_OPTIONS
-#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || ISA_HAS_BRANCHLIKELY))
+#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
/* Generate three-operand multiply instructions for both SImode and DImode. */
#define GENERATE_MULT3 (TARGET_MIPS3900 \
@@ -597,7 +598,8 @@ extern void sbss_section PARAMS ((void)
)
/* ISA has branch likely instructions (eg. mips2). */
-#define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
+#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
+ || TARGET_MIPS3900)
/* ISA has the conditional move instructions introduced in mips4. */
#define ISA_HAS_CONDMOVE (mips_isa == 4 \
@@ -909,6 +911,16 @@ while (0)
#define SUBTARGET_CC1_SPEC ""
#endif
+/* Deal with historic options. */
+#ifndef CC1_CPU_SPEC
+#define CC1_CPU_SPEC "\
+%{!mcpu*: \
+%{m3900:-mcpu=r3900 -mips1 -mfp32 -mgp32 \
+%n`-m3900' is deprecated. Use `-march=r3900' or `-mcpu=r3900' instead.\n} \
+%{m4650:-mcpu=r4650 -mmad -msingle-float \
+%n`-m4650' is deprecated. Use `-march=r4650' or `-mcpu=r4650' instead.\n}}"
+#endif
+
/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
#ifndef CC1_SPEC
@@ -920,15 +932,14 @@ while (0)
%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
%{mint64|mlong64|mlong32:-mexplicit-type-size }\
-%{m4650:-mcpu=r4650} \
-%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
%{pic-none: -mno-half-pic} \
%{pic-lib: -mhalf-pic} \
%{pic-extern: -mhalf-pic} \
%{pic-calls: -mhalf-pic} \
%{save-temps: } \
-%(subtarget_cc1_spec) "
+%(subtarget_cc1_spec) \
+%(cc1_cpu_spec)"
#endif
/* Preprocessor specs. */