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i386 floaddi?f fix
- To: gcc-patches at gcc dot gnu dot org, patches at x86-64 dot org, rth at cygnus dot com
- Subject: i386 floaddi?f fix
- From: Jan Hubicka <jh at suse dot cz>
- Date: Mon, 4 Jun 2001 17:23:16 +0200
Hi,
while cut&pasting the SImode->floats code to DImode->floats SSE
converison, I've forgot to disable some paths preventing from
using this instruction on 32bit machine, where it don't exist,
resulting in incorrect instruction to be output in some circmuatems.
Honza
Mon Jun 4 17:17:49 CEST 2001 Jan Hubicka <jh@suse.cz>
* i386.md (floatdi?f): Avoid usinf of SSE instructions
if TARGET_64BIT is false.
(floatdi?f_i386_only): New insn.
(floatdi?f_i386): Disable for !TARGET_64BIT.
Index: gcc/config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.270
diff -c -3 -p -r1.270 i386.md
*** i386.md 2001/05/17 00:53:25 1.270
--- i386.md 2001/06/04 14:45:53
***************
*** 4721,4727 ****
"TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
"
{
! if (TARGET_SSE2)
{
rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
--- 4721,4727 ----
"TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
"
{
! if (TARGET_SSE2 && TARGET_64BIT)
{
rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
***************
*** 4746,4752 ****
"TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
"
{
! if (TARGET_SSE2)
{
rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
--- 4746,4752 ----
"TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
"
{
! if (TARGET_SSE2 && TARGET_64BIT)
{
rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
***************
*** 5070,5079 ****
"(TARGET_SSE && TARGET_64BIT) || TARGET_80387"
"")
(define_insn "*floatdisf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f,?f,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
! "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
"@
fild%z1\\t%1
#
--- 5070,5090 ----
"(TARGET_SSE && TARGET_64BIT) || TARGET_80387"
"")
+ (define_insn "*floatdisf2_i387_only"
+ [(set (match_operand:SF 0 "register_operand" "=f,?f")
+ (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
+ "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
+ "@
+ fild%z1\\t%1
+ #"
+ [(set_attr "type" "fmov,multi")
+ (set_attr "mode" "SF")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatdisf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f,?f,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
! "TARGET_80387 && TARGET_64BIT && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
"@
fild%z1\\t%1
#
***************
*** 5135,5144 ****
"TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
"")
(define_insn "*floatdidf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
! "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
"@
fild%z1\\t%1
#
--- 5146,5166 ----
"TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
"")
+ (define_insn "*floatdidf2_i387_only"
+ [(set (match_operand:DF 0 "register_operand" "=f,?f")
+ (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
+ "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
+ "@
+ fild%z1\\t%1
+ #"
+ [(set_attr "type" "fmov,multi")
+ (set_attr "mode" "DF")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "*floatdidf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
! "TARGET_80387 && TARGET_64BIT && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
"@
fild%z1\\t%1
#