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Re: [bugs] Internal compiler error
- To: Jan Hubicka <jh at suse dot cz>
- Subject: Re: [bugs] Internal compiler error
- From: Jan Hubicka <jh at suse dot cz>
- Date: Thu, 24 May 2001 14:55:27 +0200
- Cc: Egbert Eich <eich at suse dot de>, bugs at x86-64 dot org, patches at x86-64 dot org, gcc-patches at gcc dot gnu dot org, rth at cygnus dot com
- References: <15114.26849.378394.70282@deepthought.fra.suse.de> <20010522154118.B31838@atrey.karlin.mff.cuni.cz> <15115.30137.153310.422892@deepthought.fra.suse.de> <20010524140833.E23324@atrey.karlin.mff.cuni.cz>
> > cd ../objects; /opt/x86-64/bin/gcc -I../ncurses -I../../ncurses-5.2/ncurses -D
> > NDEBUG -I. -I../include -I../../ncurses-5.2/ncurses/../include -I/opt/x86-64/x86
> > _64-unknown-linux//include -DHAVE_CONFIG_H -O2 -c ../../ncurses-5.2/ncurses/bas
> > e/lib_addch.c
> > ../../ncurses-5.2/ncurses/base/lib_addch.c: In function `_nc_render':
> > ../../ncurses-5.2/ncurses/base/lib_addch.c:93: Insn does not satisfy its constra
> > ints:
> > (insn/i 54 117 55 (parallel[
> > (set (zero_extract:SI (reg:SI 4 esi)
> > (const_int 8 [0x8])
> > (const_int 8 [0x8]))
> > (xor:SI (zero_extract:SI (reg:SI 4 esi)
> > (const_int 8 [0x8])
> > (const_int 8 [0x8]))
> > (zero_extract:SI (reg:SI 4 esi)
> > (const_int 8 [0x8])
> > (const_int 8 [0x8]))))
> > (clobber (reg:CC 17 flags))
> > ] ) 333 {*xorqi_ext_1} (insn_list 117 (nil))
> > (expr_list:REG_UNUSED (reg:CC 17 flags)
> > (nil)))
> > ../../ncurses-5.2/ncurses/base/lib_addch.c:93: Internal compiler error in extrac
> > t_constrain_insn_cached, at recog.c:2253
> This should not be that dificult to debug. Can you send me the preprocessed file?
Hi,
while waiting for the testcase I've take a look at the code and
found few problems.
The ext_register_operand is sometimes used even for operands that
do not take upper half. Also I've found the splitter most that
most probably caused the failure.
The patch fixes the problems by moving most of logic to ext_register_operand
and use it consistently along i386.md for (and only for) operands that are
zero_extracted to get upper half of HImode register.
Bootstraps fine on i386 in our tree, I am just testing the mainline.
OK, assuming it passes?
Honza
Thu May 24 14:49:54 CEST 2001 Jan Hubicka <jh@suse.cz>
* i386.c (ext_register_operand): Accept only the hard registers
that do have upper half register.
* i386.md (comqi_ext_1_rex64): Use register_operand.
(movqi_ext_2): Likewise.
(testqi_ext_1): Likewise.
(andqi_ext_3 peep2): Likewise.
(addqi_ext_1): Use 'Q' constraint instead of 'q'.
(testqi to testqi_ext_1 splitter): Use ext_register_operand.
Index: config/i386/i386.c
===================================================================
RCS file: /home/cvs/Repository/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.72
diff -c -3 -p -r1.72 i386.c
*** config/i386/i386.c 2001/05/22 12:45:15 1.72
--- config/i386/i386.c 2001/05/24 11:49:28
*************** ext_register_operand (op, mode)
*** 2681,2690 ****
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
if ((!TARGET_64BIT || GET_MODE (op) != DImode)
&& GET_MODE (op) != SImode && GET_MODE (op) != HImode)
return 0;
! return register_operand (op, VOIDmode);
}
/* Return 1 if this is a valid binary floating-point operation.
--- 2681,2703 ----
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
+ int regno;
if ((!TARGET_64BIT || GET_MODE (op) != DImode)
&& GET_MODE (op) != SImode && GET_MODE (op) != HImode)
return 0;
!
! /* Meaningfull usage of this predicate is only the VOIDmode
! one. */
! if (mode != VOIDmode)
! abort ();
!
! if (!register_operand (op, VOIDmode))
! return 0;
!
! /* Be curefull to accept only registers having upper parts. */
! regno = REG_P (op) ? REGNO (op) : REGNO (SUBREG_REG (op));
! if (regno > LAST_VIRTUAL_REGISTER || regno <= 4)
! return 1;
}
/* Return 1 if this is a valid binary floating-point operation.
Index: config/i386/i386.md
===================================================================
RCS file: /home/cvs/Repository/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.68
diff -c -3 -p -r1.68 i386.md
*** config/i386/i386.md 2001/05/18 09:01:39 1.68
--- config/i386/i386.md 2001/05/24 11:49:32
***************
*** 1222,1228 ****
(define_insn "*cmpqi_ext_1_rex64"
[(set (reg 17)
(compare
! (match_operand:QI 0 "ext_register_operand" "Q")
(subreg:QI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "Q")
--- 1222,1228 ----
(define_insn "*cmpqi_ext_1_rex64"
[(set (reg 17)
(compare
! (match_operand:QI 0 "register_operand" "Q")
(subreg:QI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "Q")
***************
*** 2329,2335 ****
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
! (match_operand:SI 1 "ext_register_operand" "Q"))]
"TARGET_64BIT"
"mov{b}\\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
--- 2329,2335 ----
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
! (match_operand:SI 1 "register_operand" "Q"))]
"TARGET_64BIT"
"mov{b}\\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
***************
*** 6810,6816 ****
(define_insn "addqi_ext_1"
! [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
(const_int 8)
(const_int 8))
(plus:SI
--- 6810,6816 ----
(define_insn "addqi_ext_1"
! [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(plus:SI
***************
*** 6818,6824 ****
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
! (match_operand:QI 2 "general_operand" "qmn")))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
"*
--- 6818,6824 ----
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
! (match_operand:QI 2 "general_operand" "Qmn")))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
"*
***************
*** 8121,8127 ****
(const_int 8)
(const_int 8))
(zero_extend:SI
! (match_operand:QI 1 "ext_register_operand" "Q")))
(const_int 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"test{b}\\t{%1, %h0|%h0, %1}"
--- 8121,8127 ----
(const_int 8)
(const_int 8))
(zero_extend:SI
! (match_operand:QI 1 "register_operand" "Q")))
(const_int 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"test{b}\\t{%1, %h0|%h0, %1}"
***************
*** 8371,8384 ****
"operands[1] = gen_lowpart (QImode, operands[0]);")
(define_split
! [(set (match_operand 0 "register_operand" "")
(and (match_dup 0)
(const_int -65281)))
(clobber (reg:CC 17))]
! "(optimize_size || !TARGET_PARTIAL_REG_STALL)
! && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
! || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
! && (! reload_completed || ANY_QI_REG_P (operands[0]))"
[(parallel [(set (zero_extract:SI (match_dup 0)
(const_int 8)
(const_int 8))
--- 8371,8381 ----
"operands[1] = gen_lowpart (QImode, operands[0]);")
(define_split
! [(set (match_operand 0 "ext_register_operand" "")
(and (match_dup 0)
(const_int -65281)))
(clobber (reg:CC 17))]
! "(optimize_size || !TARGET_PARTIAL_REG_STALL)"
[(parallel [(set (zero_extract:SI (match_dup 0)
(const_int 8)
(const_int 8))
***************
*** 8579,8585 ****
(and:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
! (const_int 8)
(const_int 8))
(match_operand 2 "const_int_operand" "n"))
(const_int 0)))
--- 8576,8582 ----
(and:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
! (const_int 8)
(const_int 8))
(match_operand 2 "const_int_operand" "n"))
(const_int 0)))
***************
*** 8627,8633 ****
(const_int 8)
(const_int 8))
(zero_extend:SI
! (match_operand:QI 2 "ext_register_operand" "Q"))))
(clobber (reg:CC 17))]
"TARGET_64BIT"
"and{b}\\t{%2, %h0|%h0, %2}"
--- 8624,8630 ----
(const_int 8)
(const_int 8))
(zero_extend:SI
! (match_operand 2 "register_operand" "Q"))))
(clobber (reg:CC 17))]
"TARGET_64BIT"
"and{b}\\t{%2, %h0|%h0, %2}"
***************
*** 16890,16899 ****
(compare
(and:SI
(zero_extract:SI
! (match_operand 0 "ext_register_operand" "q")
(const_int 8)
(const_int 8))
! (match_operand 1 "const_int_operand" "n"))
(const_int 0)))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
--- 16887,16896 ----
(compare
(and:SI
(zero_extract:SI
! (match_operand 0 "ext_register_operand" "")
(const_int 8)
(const_int 8))
! (match_operand 1 "const_int_operand" ""))
(const_int 0)))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)