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mailing list for the GCC project.
Patches for MIPS cronus processor
- To: <gcc-patches at gcc dot gnu dot org>
- Subject: Patches for MIPS cronus processor
- From: Joel Coltoff <joel at wmi dot com>
- Date: Wed, 2 May 2001 09:39:47 -0400 (EDT)
We have added a target to gcc-2.95.2. It is for mips32300-rtems-elf.
Unfortunately the folks that did the work have left the company for
pastures the same shade of green as those found here. They also did
this work without coordinating their efforts.
One of them, will call him Frank, added support for the instructions
that the MIPS cronus has that the 4700 and similar processors don't.
This is conditional moves, multiply and subtract, and integer add
using the HI/LO registers. All but integer add was already supported
for the 4650. Frank did not do anything with the configuration setup
or flags in the elf file. His setup is configured as mips64orion-rtems-elf.
The other, let's call him Pat, added the target to the config files so
that the binutils see it as a unique type. He configures his setup
as mips32300-rtems-elf. He didn't make use of the new assembly
instructions that Frank added.
I got stuck with trying to merge the two sets of changes. I think I've
done that. What I'm send along are patches to binutils and gcc plus some
new files that are needed for the new processor core type. I'm sending 4
files in all. There is a tar of new files to put into ../gcc/config/mips/*.
There is also a second of patches for files in gcc/config/mips/*. This
is because the patch for gcc fixes some files there Frank's way and some
of these changes need to be undone to support what Pat added. The final
version should not make any reference to 32364. This is a specific type
of the 32300 core.
If any of this isn't clear let me know and I'll try to help resolve it.
As I said I got stuck with merging the two sets of changes and would
like to know I've gotten it right. We did pick up a compiler for IDT
that like Frank's only spits out the new assembly instructions. Therefore,
you may already have this target complete or on your to do list.
--
Joel Coltoff
What lies behind us and what lies before us are tiny matters
compared to what lies within us.
-- Oliver Holmes
diff -rup /usr/src/gcc-2.95.2/gcc/config/mips/mips.c gcc-2.95.2/gcc/config/mips/mips.c
--- /usr/src/gcc-2.95.2/gcc/config/mips/mips.c Fri May 7 08:42:03 1999
+++ gcc-2.95.2/gcc/config/mips/mips.c Wed Nov 1 10:03:01 2000
@@ -4208,6 +4208,10 @@ override_options ()
mips_cpu = PROCESSOR_R3000;
else if (!strcmp (p, "3900"))
mips_cpu = PROCESSOR_R3900;
+ else if (!strcmp (p, "32364")) {
+ mips_cpu = PROCESSOR_R32364;
+ target_flags |= MASK_MAD | MASK_MSUB;
+ }
break;
case '4':
@@ -4269,7 +4273,9 @@ override_options ()
}
if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
- || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
+ || ((mips_cpu == PROCESSOR_R6000
+ || mips_cpu == PROCESSOR_R32364)
+ && mips_isa > 2)
|| ((mips_cpu == PROCESSOR_R4000
|| mips_cpu == PROCESSOR_R4100
|| mips_cpu == PROCESSOR_R4300
diff -rup /usr/src/gcc-2.95.2/gcc/config/mips/mips.h gcc-2.95.2/gcc/config/mips/mips.h
--- /usr/src/gcc-2.95.2/gcc/config/mips/mips.h Wed May 19 19:05:45 1999
+++ gcc-2.95.2/gcc/config/mips/mips.h Wed Nov 1 10:10:19 2000
@@ -69,7 +69,8 @@ enum processor_type {
PROCESSOR_R4600,
PROCESSOR_R4650,
PROCESSOR_R5000,
- PROCESSOR_R8000
+ PROCESSOR_R8000,
+ PROCESSOR_R32364
};
/* Recast the cpu class to be the cpu attribute. */
@@ -328,6 +329,7 @@ extern void mips_select_section ();
#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
+#define MASK_MSUB 0x00200000 /* Generate msub/msubu as on 32364 */
#define MASK_MIPS16 0x01000000 /* Generate mips16 code */
#define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
#define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
@@ -417,6 +419,7 @@ extern void mips_select_section ();
#define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
#define TARGET_MAD (target_flags & MASK_MAD)
+#define TARGET_MSUB (target_flags & MASK_MSUB)
#define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
@@ -526,6 +529,10 @@ extern void mips_select_section ();
"Use multiply accumulate"}, \
{"no-mad", -MASK_MAD, \
"Don't use multiply accumulate"}, \
+ {"msub", MASK_MSUB, \
+ "Use multiply subtract"}, \
+ {"no-msub", -MASK_MSUB, \
+ "Don't use multiply subtract"}, \
{"fix4300", MASK_4300_MUL_FIX, \
"Work around early 4300 hardware bug"}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
@@ -534,6 +541,9 @@ extern void mips_select_section ();
"Optimize for 4650"}, \
{"3900", MASK_MIPS3900, \
"Optimize for 3900"}, \
+ {"32364", (MASK_MAD | MASK_MSUB | MASK_SOFT_FLOAT \
+ | MASK_SINGLE_FLOAT), \
+ "Optimize for IDT RC32364"}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
"Trap on integer divide by zero"}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
@@ -821,7 +831,10 @@ while (0)
/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
assembler. */
-#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
+#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} \
+ %{!m32364: %{msub:-m32364} %{!msub:%{mmad:-m4650}}} \
+ %{m32364: %{!mpcu:-mcpu=32364}} \
+ %{m3900} %{v}"
/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
GAS_ASM_SPEC as the default, depending upon the value of
@@ -943,13 +956,16 @@ while (0)
#ifndef CC1_SPEC
#define CC1_SPEC "\
%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
+%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32} \
%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
%{mint64|mlong64|mlong32:-mexplicit-type-size }\
%{m4650:-mcpu=r4650} \
+%{m32364:-msoft-float -mcpu=r32364 %{!mips*:-mips2 -mgp32} \
+ %{mips4:%emay not use -m32364 and -mips4} \
+ %{mips3:%emay not use -m32364 and -mips3}} \
%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
%{pic-none: -mno-half-pic} \
@@ -1466,7 +1482,7 @@ do { \
constants can be done inline. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
- ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
+ ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
&& (ALIGN) < BITS_PER_WORD \
? BITS_PER_WORD \
: (ALIGN))
diff -rup /usr/src/gcc-2.95.2/gcc/config/mips/mips.md gcc-2.95.2/gcc/config/mips/mips.md
--- /usr/src/gcc-2.95.2/gcc/config/mips/mips.md Mon Jun 28 21:59:20 1999
+++ gcc-2.95.2/gcc/config/mips/mips.md Fri Oct 27 11:18:14 2000
@@ -82,7 +82,7 @@
;; ??? Fix everything that tests this attribute.
(define_attr "cpu"
- "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000"
+ "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000,r32364"
(const (symbol_ref "mips_cpu_attr")))
;; Does the instruction have a mandatory delay slot?
@@ -153,12 +153,12 @@
(define_function_unit "memory" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
+ (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000,r32364"))
3 0)
(define_function_unit "memory" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
+ (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000,r32364"))
2 0)
(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
@@ -171,7 +171,7 @@
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
+ (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r32364"))
17 17)
;; On them mips16, we want to stronly discourage a mult from appearing
@@ -193,7 +193,7 @@
10 10)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650"))
+ (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650,r32364"))
4 4)
(define_function_unit "imuldiv" 1 0
@@ -223,7 +223,7 @@
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
+ (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r32364"))
38 38)
(define_function_unit "imuldiv" 1 0
@@ -235,7 +235,7 @@
42 42)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650,r32364"))
36 36)
(define_function_unit "imuldiv" 1 0
@@ -2031,6 +2031,22 @@
(set_attr "mode" "SI")
(set_attr "length" "1")])
+;; The RC32364 supports a 32 bit multiply/ 64 bit subtract
+;; instruction. The HI/LO registers are used as a 64 bit accumulator.
+
+(define_insn "msubsi"
+ [(set (match_operand:SI 0 "register_operand" "+l")
+ (minus:SI (match_dup 0)
+ (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))))
+ (clobber (match_scratch:SI 3 "=h"))
+ (clobber (match_scratch:SI 4 "=a"))]
+ "TARGET_MSUB"
+ "msub\\t%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "1")])
+
(define_insn "*mul_acc_di"
[(set (match_operand:DI 0 "register_operand" "+x")
(plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
@@ -9984,7 +10000,7 @@ move\\t%0,%z4\\n\\
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
@@ -9999,7 +10015,7 @@ move\\t%0,%z4\\n\\
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
@@ -10030,7 +10046,7 @@ move\\t%0,%z4\\n\\
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
@@ -10045,7 +10061,7 @@ move\\t%0,%z4\\n\\
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
@@ -10138,7 +10154,7 @@ move\\t%0,%z4\\n\\
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand" "")
(match_operand:SI 3 "reg_or_0_operand" "")))]
- "mips_isa >= 4"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"
{
gen_conditional_move (operands);
diff -rup /usr/src/gcc-2.95.2/gcc/config/mips/t-ecoff gcc-2.95.2/gcc/config/mips/t-ecoff
--- /usr/src/gcc-2.95.2/gcc/config/mips/t-ecoff Wed Dec 16 16:09:37 1998
+++ gcc-2.95.2/gcc/config/mips/t-ecoff Fri Oct 27 10:57:38 2000
@@ -53,7 +53,7 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3
MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3
-MULTILIB_MATCHES = msingle-float=m4650
+MULTILIB_MATCHES = msingle-float=m4650 msoft-float=m32364
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
diff -rup /usr/src/binutils-2.10/bfd/archures.c binutils-2.10/bfd/archures.c
--- /usr/src/binutils-2.10/bfd/archures.c Mon Mar 27 03:39:12 2000
+++ binutils-2.10/bfd/archures.c Thu Nov 2 12:50:27 2000
@@ -127,6 +127,7 @@ DESCRIPTION
.#define bfd_mach_mips6000 6000
.#define bfd_mach_mips8000 8000
.#define bfd_mach_mips10000 10000
+.#define bfd_mach_mips32364 32364
.#define bfd_mach_mips16 16
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_i386_i386 0
diff -rup /usr/src/binutils-2.10/bfd/bfd-in2.h binutils-2.10/bfd/bfd-in2.h
--- /usr/src/binutils-2.10/bfd/bfd-in2.h Fri Apr 28 21:45:48 2000
+++ binutils-2.10/bfd/bfd-in2.h Thu Nov 2 12:50:59 2000
@@ -1343,6 +1343,7 @@ enum bfd_architecture
#define bfd_mach_mips6000 6000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips10000 10000
+#define bfd_mach_mips32364 32364
#define bfd_mach_mips16 16
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
diff -rup /usr/src/binutils-2.10/bfd/cpu-mips.c binutils-2.10/bfd/cpu-mips.c
--- /usr/src/binutils-2.10/bfd/cpu-mips.c Mon May 3 03:28:55 1999
+++ binutils-2.10/bfd/cpu-mips.c Thu Nov 2 13:20:43 2000
@@ -53,6 +53,7 @@ I_mips5000,
I_mips6000,
I_mips8000,
I_mips10000,
+I_mips32364,
I_mips16
};
@@ -75,6 +76,7 @@ static const bfd_arch_info_type arch_inf
N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
+ N (32, 32, bfd_mach_mips32364, "mips:32364", false, NN(I_mips32364)),
N (64, 64, bfd_mach_mips16, "mips:16", false, 0),
diff -rup /usr/src/binutils-2.10/bfd/doc/archures.texi binutils-2.10/bfd/doc/archures.texi
--- /usr/src/binutils-2.10/bfd/doc/archures.texi Mon May 29 10:08:51 2000
+++ binutils-2.10/bfd/doc/archures.texi Thu Nov 2 12:53:15 2000
@@ -94,6 +94,7 @@ enum bfd_architecture
#define bfd_mach_mips6000 6000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips10000 10000
+#define bfd_mach_mips32364 32364
#define bfd_mach_mips16 16
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
diff -rup /usr/src/binutils-2.10/bfd/doc/bfd.info-4 binutils-2.10/bfd/doc/bfd.info-4
--- /usr/src/binutils-2.10/bfd/doc/bfd.info-4 Sat Jun 10 08:28:05 2000
+++ binutils-2.10/bfd/doc/bfd.info-4 Thu Nov 2 12:53:43 2000
@@ -522,6 +522,7 @@ i960 KB, and 68020 and 68030 for Motorol
#define bfd_mach_mips6000 6000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips10000 10000
+ #define bfd_mach_mips32364 32364
#define bfd_mach_mips16 16
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
diff -rup /usr/src/binutils-2.10/gas/config/tc-mips.c binutils-2.10/gas/config/tc-mips.c
--- /usr/src/binutils-2.10/gas/config/tc-mips.c Fri Mar 10 21:16:25 2000
+++ binutils-2.10/gas/config/tc-mips.c Thu Nov 2 13:08:02 2000
@@ -258,12 +258,14 @@ static int mips_gp32 = 0;
-- Jim Blandy <jimb@cygnus.com> */
#define hilo_interlocks (mips_cpu == 4010 \
+ || mips_cpu == 32364 \
)
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs, and thus does not require nops to be inserted. */
#define gpr_interlocks \
(mips_opts.isa != 1 \
+ || mips_cpu == 32364 \
|| mips_cpu == 3900)
/* As with other "interlocks" this is used by hardware that has FP
@@ -947,6 +949,9 @@ md_begin ()
else if (strcmp (cpu, "mips16") == 0)
mips_cpu = 0; /* FIXME */
+ else if (strcmp (cpu, "r32364") == 0)
+ mips_cpu = 32364;
+
else
mips_cpu = 3000;
}
@@ -956,7 +961,8 @@ md_begin ()
mips_isa_from_cpu = 1;
else if (mips_cpu == 6000
- || mips_cpu == 4010)
+ || mips_cpu == 4010
+ || mips_cpu == 32364)
mips_isa_from_cpu = 2;
else if (mips_cpu == 4000
@@ -8854,6 +8860,10 @@ struct option md_longopts[] = {
{"m3900", no_argument, NULL, OPTION_M3900},
#define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
{"no-m3900", no_argument, NULL, OPTION_NO_M3900},
+#define OPTION_M32364 (OPTION_MD_BASE + 28)
+ {"m32364", no_argument, NULL, OPTION_M32364},
+#define OPTION_NO_M32364 (OPTION_MD_BASE + 29)
+ {"no-m32364", no_argument, NULL, OPTION_NO_M32364},
#define OPTION_MABI (OPTION_MD_BASE + 38)
@@ -8993,6 +9003,8 @@ md_parse_option (c, arg)
mips_cpu = 3000;
else if (strcmp (p, "3900") == 0)
mips_cpu = 3900;
+ else if (strcmp (p, "32364") == 0)
+ mips_cpu = 32364;
break;
case '4':
@@ -9091,6 +9103,13 @@ md_parse_option (c, arg)
case OPTION_NO_M3900:
break;
+ case OPTION_M32364:
+ mips_cpu = 32364;
+ break;
+
+ case OPTION_NO_M32364:
+ break;
+
case OPTION_MIPS16:
mips_opts.mips16 = 1;
mips_no_prev_insn (false);
@@ -9299,6 +9318,7 @@ MIPS options:\n\
show (stream, "6000", &column, &first);
show (stream, "8000", &column, &first);
show (stream, "10000", &column, &first);
+ show (stream, "32364", &column, &first);
fputc ('\n', stream);
fprintf (stream, _("\
@@ -9312,6 +9332,7 @@ MIPS options:\n\
show (stream, "4010", &column, &first);
show (stream, "4100", &column, &first);
show (stream, "4650", &column, &first);
+ show (stream, "32364", &column, &first);
fputc ('\n', stream);
fprintf(stream, _("\
diff -rup /usr/src/binutils-2.10/include/opcode/mips.h binutils-2.10/include/opcode/mips.h
--- /usr/src/binutils-2.10/include/opcode/mips.h Tue Feb 22 14:01:25 2000
+++ binutils-2.10/include/opcode/mips.h Thu Nov 2 13:11:19 2000
@@ -319,6 +319,8 @@ struct mips_opcode
#define INSN_4100 0x00000040
/* Toshiba R3900 instruction. */
#define INSN_3900 0x00000080
+/* IDT RC32364 instruction. */
+#define INSN_32364 0x00000100
/* 32-bit code running on a ISA3+ CPU. */
#define INSN_GP32 0x00001000
@@ -344,7 +346,9 @@ struct mips_opcode
) \
&& ((insn)->membership & INSN_4100) != 0) \
|| (cpu == 3900 \
- && ((insn)->membership & INSN_3900) != 0))
+ && ((insn)->membership & INSN_3900) != 0) \
+ || (cpu == 32364 \
+ && ((insn)->membership & INSN_32364) != 0))
/* This is a list of macro expanded instructions.
*
diff -rup /usr/src/binutils-2.10/opcodes/mips-dis.c binutils-2.10/opcodes/mips-dis.c
--- /usr/src/binutils-2.10/opcodes/mips-dis.c Sat May 6 10:49:26 2000
+++ binutils-2.10/opcodes/mips-dis.c Thu Nov 2 13:12:33 2000
@@ -311,6 +311,10 @@ set_mips_isa_type (mach, isa, cputype)
target_processor = 10000;
mips_isa = 4;
break;
+ case bfd_mach_mips32364:
+ target_processor = 32364;
+ mips_isa = 2;
+ break;
case bfd_mach_mips16:
target_processor = 16;
mips_isa = 3;
diff -rup /usr/src/binutils-2.10/opcodes/mips-opc.c binutils-2.10/opcodes/mips-opc.c
--- /usr/src/binutils-2.10/opcodes/mips-opc.c Sat May 6 10:49:26 2000
+++ binutils-2.10/opcodes/mips-opc.c Thu Nov 2 13:50:20 2000
@@ -81,6 +81,7 @@ Software Foundation, 59 Temple Place - S
#define L1 INSN_4010
#define V1 INSN_4100
#define T3 INSN_3900
+#define C1 INSN_32364
#define G1 (T3 \
)
@@ -317,7 +318,7 @@ const struct mips_opcode mips_builtin_op
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
-{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1 },
+{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1|C1 },
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
@@ -327,6 +328,8 @@ const struct mips_opcode mips_builtin_op
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
+{"clo", "s,t", 0x70000021, 0xfc00ffff, RD_s|WR_t, C1 },
+{"clz", "s,t", 0x70000020, 0xfc00ffff, RD_s|WR_t, C1 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
@@ -427,7 +430,8 @@ const struct mips_opcode mips_builtin_op
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
-{"eret", "", 0x42000018, 0xffffffff, 0, I3|M1 },
+{"dret", "", 0x4200001f, 0xffffffff, 0, C1 },
+{"eret", "", 0x42000018, 0xffffffff, 0, I3|M1|C1 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
@@ -526,8 +530,8 @@ const struct mips_opcode mips_builtin_op
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
-{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
-{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
+{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|C1 },
+{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|C1 },
{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
@@ -552,7 +556,7 @@ const struct mips_opcode mips_builtin_op
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 },
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1 },
+{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|C1 },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 },
@@ -560,7 +564,7 @@ const struct mips_opcode mips_builtin_op
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 },
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5},
-{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1 },
+{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|C1 },
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 },
@@ -569,7 +573,9 @@ const struct mips_opcode mips_builtin_op
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
+{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, C1 },
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
+{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, C1 },
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
@@ -580,7 +586,7 @@ const struct mips_opcode mips_builtin_op
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
-{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3},
+{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3|C1},
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
@@ -613,7 +619,7 @@ const struct mips_opcode mips_builtin_op
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
-{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1 },
+{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|C1 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
@@ -647,9 +653,9 @@ const struct mips_opcode mips_builtin_op
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 },
-{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
-{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
-{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
+{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1|C1 },
+{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1|C1 },
+{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1|C1 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
@@ -801,7 +807,7 @@ const struct mips_opcode mips_builtin_op
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
-{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1 },
+{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|C1 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
/* No hazard protection on coprocessor instructions--they shouldn't
diff -rup ./ecoff.h /project/cross-gcc/src/gcc/config/mips/ecoff.h
--- ./ecoff.h Tue Apr 3 11:27:40 2001
+++ /project/cross-gcc/src/gcc/config/mips/ecoff.h Tue Nov 21 16:28:46 2000
@@ -24,9 +24,8 @@ Boston, MA 02111-1307, USA. */
#include "mips/mips.h"
-#ifndef CPP_PREDEFINES
+#undef CPP_PREDEFINES
#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR3000 -D_mips -D_MIPSEB -D_R3000"
-#endif
/* Use memcpy, et. al., rather than bcopy. */
#define TARGET_MEM_FUNCTIONS
diff -rup ./elf64.h /project/cross-gcc/src/gcc/config/mips/elf64.h
--- ./elf64.h Mon Apr 2 12:21:24 2001
+++ /project/cross-gcc/src/gcc/config/mips/elf64.h Tue Nov 21 16:28:46 2000
@@ -53,7 +53,7 @@ Boston, MA 02111-1307, USA. */
doesn't handle -U options in CPP_PREDEFINES. */
#undef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC "\
-%{!mips1:%{!mips2: %{!m32300: -U__mips -D__mips=3 -D__mips64}}}"
+%{!mips1:%{!mips2: %{!m32364: -U__mips -D__mips=3 -D__mips64}}}"
/* Use memcpy, et. al., rather than bcopy. */
#define TARGET_MEM_FUNCTIONS
diff -rup ./mips.c /project/cross-gcc/src/gcc/config/mips/mips.c
--- ./mips.c Tue Apr 3 11:31:54 2001
+++ /project/cross-gcc/src/gcc/config/mips/mips.c Tue Nov 21 16:28:46 2000
@@ -4208,9 +4208,9 @@ override_options ()
mips_cpu = PROCESSOR_R3000;
else if (!strcmp (p, "3900"))
mips_cpu = PROCESSOR_R3900;
- else if (!strcmp (p, "32300")) {
- mips_cpu = PROCESSOR_R32300;
- target_flags |= MASK_MIPS32300 | MASK_MAD | MASK_MSUB | MASK_SOFT_FLOAT;
+ else if (!strcmp (p, "32364")) {
+ mips_cpu = PROCESSOR_R32364;
+ target_flags |= MASK_MAD | MASK_MSUB;
}
break;
@@ -4274,7 +4274,7 @@ override_options ()
if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
|| ((mips_cpu == PROCESSOR_R6000
- || mips_cpu == PROCESSOR_R32300)
+ || mips_cpu == PROCESSOR_R32364)
&& mips_isa > 2)
|| ((mips_cpu == PROCESSOR_R4000
|| mips_cpu == PROCESSOR_R4100
diff -rup ./mips.h /project/cross-gcc/src/gcc/config/mips/mips.h
--- ./mips.h Tue Apr 3 11:44:32 2001
+++ /project/cross-gcc/src/gcc/config/mips/mips.h Tue Nov 21 16:28:46 2000
@@ -70,7 +70,7 @@ enum processor_type {
PROCESSOR_R4650,
PROCESSOR_R5000,
PROCESSOR_R8000,
- PROCESSOR_R32300
+ PROCESSOR_R32364
};
/* Recast the cpu class to be the cpu attribute. */
@@ -329,8 +329,7 @@ extern void mips_select_section ();
#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
-#define MASK_MSUB 0x00200000 /* Generate msub/msubu as on 32300 */
-#define MASK_MIPS32300 0x00400000 /* like -mips2 only 32300 */
+#define MASK_MSUB 0x00200000 /* Generate msub/msubu as on 32364 */
#define MASK_MIPS16 0x01000000 /* Generate mips16 code */
#define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
#define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
@@ -362,9 +361,6 @@ extern void mips_select_section ();
/* generate mips 3900 insns */
#define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
-/* generate mips 32300 insns */
-#define TARGET_MIPS32300 (target_flags & MASK_MIPS32300)
-
/* Mips vs. GNU assembler */
#define TARGET_GAS (target_flags & MASK_GAS)
#define TARGET_UNIX_ASM (!TARGET_GAS)
@@ -545,9 +541,9 @@ extern void mips_select_section ();
"Optimize for 4650"}, \
{"3900", MASK_MIPS3900, \
"Optimize for 3900"}, \
- {"32300", (MASK_MIPS32300 | MASK_MAD | MASK_MSUB | \
- MASK_SOFT_FLOAT ), \
- "Optimize for IDT RC32300"}, \
+ {"32364", (MASK_MAD | MASK_MSUB | MASK_SOFT_FLOAT \
+ | MASK_SINGLE_FLOAT), \
+ "Optimize for IDT RC32364"}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
"Trap on integer divide by zero"}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
@@ -836,8 +832,8 @@ while (0)
assembler. */
#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} \
- %{!m32300: %{msub:-m32300} %{!msub:%{mmad:-m4650}}} \
- %{m32300: %{!mpcu:-mcpu=32300} %{!mips*: -mips2}} \
+ %{!m32364: %{msub:-m32364} %{!msub:%{mmad:-m4650}}} \
+ %{m32364: %{!mpcu:-mcpu=32364} %{!mips*: -mips2}} \
%{m3900} %{v}"
/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
@@ -967,9 +963,9 @@ while (0)
%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
%{mint64|mlong64|mlong32:-mexplicit-type-size }\
%{m4650:-mcpu=r4650} \
-%{m32300:-msoft-float -mcpu=r32300 %{!mips*:-mips2 -mgp32} \
- %{mips4:%emay not use -m32300 and -mips4} \
- %{mips3:%emay not use -m32300 and -mips3}} \
+%{m32364:-msoft-float -mcpu=r32364 %{!mips*:-mips2 -mgp32} \
+ %{mips4:%emay not use -m32364 and -mips4} \
+ %{mips3:%emay not use -m32364 and -mips3}} \
%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
%{pic-none: -mno-half-pic} \
diff -rup ./mips.md /project/cross-gcc/src/gcc/config/mips/mips.md
--- ./mips.md Mon Apr 2 12:22:09 2001
+++ /project/cross-gcc/src/gcc/config/mips/mips.md Tue Nov 21 16:28:46 2000
@@ -82,7 +82,7 @@
;; ??? Fix everything that tests this attribute.
(define_attr "cpu"
- "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000,r32300"
+ "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000,r32364"
(const (symbol_ref "mips_cpu_attr")))
;; Does the instruction have a mandatory delay slot?
@@ -153,12 +153,12 @@
(define_function_unit "memory" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000,r32300"))
+ (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000,r32364"))
3 0)
(define_function_unit "memory" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000,r32300"))
+ (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000,r32364"))
2 0)
(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
@@ -171,7 +171,7 @@
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r32300"))
+ (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r32364"))
17 17)
;; On them mips16, we want to stronly discourage a mult from appearing
@@ -193,7 +193,7 @@
10 10)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650,r32300"))
+ (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650,r32364"))
4 4)
(define_function_unit "imuldiv" 1 0
@@ -223,7 +223,7 @@
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r32300"))
+ (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r32364"))
38 38)
(define_function_unit "imuldiv" 1 0
@@ -235,7 +235,7 @@
42 42)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650,r32300"))
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650,r32364"))
36 36)
(define_function_unit "imuldiv" 1 0
@@ -2031,7 +2031,7 @@
(set_attr "mode" "SI")
(set_attr "length" "1")])
-;; The RC32300 supports a 32 bit multiply/ 64 bit subtract
+;; The RC32364 supports a 32 bit multiply/ 64 bit subtract
;; instruction. The HI/LO registers are used as a 64 bit accumulator.
(define_insn "msubsi"
@@ -10000,7 +10000,7 @@ move\\t%0,%z4\\n\\
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4 || mips_cpu == PROCESSOR_R32300"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
@@ -10015,7 +10015,7 @@ move\\t%0,%z4\\n\\
(const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4 || mips_cpu == PROCESSOR_R32300"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
@@ -10046,7 +10046,7 @@ move\\t%0,%z4\\n\\
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4 || mips_cpu == PROCESSOR_R32300"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
@@ -10061,7 +10061,7 @@ move\\t%0,%z4\\n\\
(const_int 0)])
(match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
- "mips_isa >= 4 || mips_cpu == PROCESSOR_R32300"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"@
mov%B4\\t%0,%z2,%1
mov%b4\\t%0,%z3,%1"
@@ -10154,7 +10154,7 @@ move\\t%0,%z4\\n\\
(if_then_else:SI (match_dup 5)
(match_operand:SI 2 "reg_or_0_operand" "")
(match_operand:SI 3 "reg_or_0_operand" "")))]
- "mips_isa >= 4 || mips_cpu == PROCESSOR_R32300"
+ "mips_isa >= 4 || mips_cpu == PROCESSOR_R32364"
"
{
gen_conditional_move (operands);
diff -rup ./t-ecoff /project/cross-gcc/src/gcc/config/mips/t-ecoff
--- ./t-ecoff Tue Apr 3 11:40:55 2001
+++ /project/cross-gcc/src/gcc/config/mips/t-ecoff Tue Nov 21 16:28:46 2000
@@ -53,7 +53,7 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3
MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3
-MULTILIB_MATCHES = msingle-float=m4650
+MULTILIB_MATCHES = msingle-float=m4650 msoft-float=m32364
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
diff -rup ./t-elf /project/cross-gcc/src/gcc/config/mips/t-elf
--- ./t-elf Tue Apr 3 11:42:29 2001
+++ /project/cross-gcc/src/gcc/config/mips/t-elf Tue Nov 21 16:28:46 2000
@@ -55,9 +55,10 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
# Build the libraries for both hard and soft floating point
-MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3
-MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3
-MULTILIB_MATCHES = msingle-float=m4650
+MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/m32364/mips3
+MULTILIB_DIRNAMES = soft-float single el eb mips1 m32364 mips3
+MULTILIB_MATCHES = msingle-float=m4650 msoft-float=m32364
+MULTILIB_EXCEPTIONS = m32364 msingle-float/m32364 EL/m32364 msingle-float/EL/m32364
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
gcc-r32300.tar