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Fix for SSE conditional moves



Hi,
it has turned out that there are quite a few bugs on the way. tThe matching constraint
is bogues in one of copies of SSE conditional move patterns and the splitter gets
completely confused on second alternative. I also believe that we can't use
rtx_equal_p for testing whehter operand match, since unlike on insn patterns no noe
take care to make them actually equivalent.

This patch should make SSE conditional moves finally functional (:-)
I am going to install it to x86_64 tree and wait for approval in mainline.

Andreas: The previous gcc was broken too (even the source you sent me) so the tests probably
worked by luck.

Honza

Wed Mar 28 19:36:14 CEST 2001  Jan Hubicka  <jh@suse.cz>
	* i386.md (sse_movdfcc_eq): Fix constraint
	(sse_mov?fcc splitter): Use operands_match_p instead of rtx_equal_p;
	fix the output template.

Index: i386.md
===================================================================
RCS file: /home/cvs/Repository/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.42
diff -c -3 -p -r1.42 i386.md
*** i386.md	2001/03/26 15:37:37	1.42
--- i386.md	2001/03/28 18:01:39
***************
*** 15737,15743 ****
  			     (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
  		      (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
  		      (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
!    (clobber (match_scratch:SF 5 "=1,&4,X,X,X,X"))
     (clobber (reg:CC 17))]
    "TARGET_SSE
     && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
--- 15737,15743 ----
  			     (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
  		      (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
  		      (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
!    (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
     (clobber (reg:CC 17))]
    "TARGET_SSE
     && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
***************
*** 15810,15827 ****
    "SSE_REG_P (operands[0]) && reload_completed"
    [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
     (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
! 					    (subreg:TI (match_dup 0) 0)))
!    (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 0) 0))
  					    (subreg:TI (match_dup 3) 0)))
     (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
  					    (subreg:TI (match_dup 7) 0)))]
    "
  {
    PUT_MODE (operands[1], GET_MODE (operands[0]));
!   if (rtx_equal_p (operands[0], operands[4]))
      operands[6] = operands[4], operands[7] = operands[2];
    else
!     operands[6] = operands[2], operands[7] = operands[0];
  }")
  
  ;; Special case of conditional move we can handle effectivly.
--- 15810,15827 ----
    "SSE_REG_P (operands[0]) && reload_completed"
    [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
     (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
! 					    (subreg:TI (match_dup 4) 0)))
!    (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
  					    (subreg:TI (match_dup 3) 0)))
     (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
  					    (subreg:TI (match_dup 7) 0)))]
    "
  {
    PUT_MODE (operands[1], GET_MODE (operands[0]));
!   if (operands_match_p (operands[0], operands[4]))
      operands[6] = operands[4], operands[7] = operands[2];
    else
!     operands[6] = operands[2], operands[7] = operands[4];
  }")
  
  ;; Special case of conditional move we can handle effectivly.


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