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Patches for 128 bit float support on IA64 HP-UX
- To: gcc-patches at gcc dot gnu dot org
- Subject: Patches for 128 bit float support on IA64 HP-UX
- From: Steve Ellcey <sje at cup dot hp dot com>
- Date: Mon, 26 Mar 2001 09:49:44 -0800 (PST)
- Reply-To: sje at cup dot hp dot com
This set of changes is to support 128 bit floating point on IA64 HP-UX.
This is needed to match the HP compiler on IA64, many of the changes are
copied from the 128 bit support that was done for the PA HP-UX platform.
Except for config.gcc all the changes are in the gcc/config/ia64, but it
does affect more of the generic ia64 files used by linux then the
original hp-ux checkin did.
Ideally, I'd like to have this checked in to the 3.0 branch as well as
the main line so that the 3.0 IA64 GCC compiler, when it is released, is
compatible with the HP-UX compiler in its treatment of long double.
Steve Ellcey
sje@cup.hp.com
*** config.gcc.orig Mon Mar 26 08:50:30 2001
--- config.gcc Thu Mar 22 13:11:21 2001
*************** ia64*-*-linux*)
*** 1606,1612 ****
float_format=i386
;;
ia64*-*-hpux*)
! tm_file="ia64/ia64.h svr4.h ia64/sysv4.h ia64/hpux.h"
tmake_file="ia64/t-ia64 ia64/t-hpux"
target_cpu_default="MASK_GNU_AS"
if test x$enable_threads = xyes; then
--- 1606,1612 ----
float_format=i386
;;
ia64*-*-hpux*)
! tm_file="ia64/hpux_longdouble.h ia64/ia64.h svr4.h ia64/sysv4.h ia64/hpux.h"
tmake_file="ia64/t-ia64 ia64/t-hpux"
target_cpu_default="MASK_GNU_AS"
if test x$enable_threads = xyes; then
*** config/ia64/ia64.h.orig Mon Mar 26 08:51:06 2001
--- config/ia64/ia64.h Fri Mar 23 16:10:25 2001
*************** while (0)
*** 469,475 ****
--- 469,480 ----
/* Tell real.c that this is the 80-bit Intel extended float format
packaged in a 128-bit entity. */
+ #ifndef FULL_LONG_DOUBLE_FORMAT
#define INTEL_EXTENDED_IEEE_FORMAT
+ #define TARGET_80LD 1
+ #else
+ #define TARGET_80LD 0
+ #endif
/* An expression whose value is 1 or 0, according to whether the type `char'
should be signed or unsigned by default. The user can always override this
*************** while (0)
*** 823,829 ****
((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
! : FR_REGNO_P (REGNO) && (MODE) == TFmode ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* A C expression that is nonzero if it is permissible to store a value of mode
--- 828,834 ----
((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
! : FR_REGNO_P (REGNO) && (MODE) == TFmode && TARGET_80LD ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* A C expression that is nonzero if it is permissible to store a value of mode
*************** while (0)
*** 832,838 ****
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(FR_REGNO_P (REGNO) ? \
! GET_MODE_CLASS (MODE) != MODE_CC && (MODE) != TImode && (MODE) != BImode \
: PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
: GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
--- 837,846 ----
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(FR_REGNO_P (REGNO) ? \
! GET_MODE_CLASS (MODE) != MODE_CC && \
! (MODE) != TImode && \
! (MODE) != BImode && \
! ((MODE) != TFmode || TARGET_80LD) \
: PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
: GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
*************** do { \
*** 1418,1425 ****
#define LIBCALL_VALUE(MODE) \
gen_rtx_REG (MODE, \
! ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
! || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
? FR_RET_FIRST : GR_RET_FIRST))
/* A C expression that is nonzero if REGNO is the number of a hard register in
--- 1426,1434 ----
#define LIBCALL_VALUE(MODE) \
gen_rtx_REG (MODE, \
! (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
! || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
! ((MODE) != TFmode || TARGET_80LD)) \
? FR_RET_FIRST : GR_RET_FIRST))
/* A C expression that is nonzero if REGNO is the number of a hard register in
*** config/ia64/ia64.c.orig Mon Mar 26 08:51:06 2001
--- config/ia64/ia64.c Fri Mar 23 16:26:49 2001
*************** ia64_function_arg (cum, mode, type, name
*** 2856,2862 ****
/* Integral and aggregates go in general registers. If we have run out of
FR registers, then FP values must also go in general registers. This can
happen when we have a SFmode HFA. */
! else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
return gen_rtx_REG (mode, basereg + cum->words + offset);
/* If there is a prototype, then FP values go in a FR register when
--- 2856,2863 ----
/* Integral and aggregates go in general registers. If we have run out of
FR registers, then FP values must also go in general registers. This can
happen when we have a SFmode HFA. */
! else if (((mode == TFmode) && (!TARGET_80LD))
! || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
return gen_rtx_REG (mode, basereg + cum->words + offset);
/* If there is a prototype, then FP values go in a FR register when
*************** ia64_function_value (valtype, func)
*** 3136,3142 ****
else
return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
}
! else if (FLOAT_TYPE_P (valtype))
return gen_rtx_REG (mode, FR_ARG_FIRST);
else
return gen_rtx_REG (mode, GR_RET_FIRST);
--- 3137,3144 ----
else
return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
}
! else if (((mode != TFmode) || (TARGET_80LD)) &&
! (FLOAT_TYPE_P (valtype)))
return gen_rtx_REG (mode, FR_ARG_FIRST);
else
return gen_rtx_REG (mode, GR_RET_FIRST);
*** config/ia64/ia64.md.orig Mon Mar 26 08:51:06 2001
--- config/ia64/ia64.md Thu Mar 22 13:27:25 2001
***************
*** 678,684 ****
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" ""))]
! ""
"
{
/* We must support TFmode loads into general registers for stdarg/vararg
--- 678,684 ----
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")
(match_operand:TF 1 "general_operand" ""))]
! "TARGET_80LD"
"
{
/* We must support TFmode loads into general registers for stdarg/vararg
***************
*** 750,756 ****
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
! "ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
--- 750,756 ----
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
(match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
! "TARGET_80LD && ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
***************
*** 854,860 ****
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
(float_extend:TF
(match_operand:SF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
! ""
"@
mov %0 = %1
mov %0 = %1
--- 854,860 ----
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
(float_extend:TF
(match_operand:SF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
! "TARGET_80LD"
"@
mov %0 = %1
mov %0 = %1
***************
*** 877,883 ****
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
(float_extend:TF
(match_operand:DF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
! ""
"@
mov %0 = %1
mov %0 = %1
--- 877,883 ----
[(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
(float_extend:TF
(match_operand:DF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
! "TARGET_80LD"
"@
mov %0 = %1
mov %0 = %1
***************
*** 906,919 ****
(define_insn "trunctfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
! ""
"fnorm.s %0 = %1"
[(set_attr "itanium_class" "fmac")])
(define_insn "trunctfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
! ""
"fnorm.d %0 = %1"
[(set_attr "itanium_class" "fmac")])
--- 906,919 ----
(define_insn "trunctfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fnorm.s %0 = %1"
[(set_attr "itanium_class" "fmac")])
(define_insn "trunctfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fnorm.d %0 = %1"
[(set_attr "itanium_class" "fmac")])
***************
*** 922,931 ****
(define_insn "floatditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
! ""
"fcvt.xf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
--- 922,945 ----
(define_insn "floatditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fcvt.xf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
+ (define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (float:DF (match_operand:DI 1 "register_operand" "f")))]
+ "!TARGET_80LD"
+ "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0"
+ [(set_attr "itanium_class" "fcvtfx")])
+
+ (define_insn "floatdisf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (float:SF (match_operand:DI 1 "register_operand" "f")))]
+ "!TARGET_80LD"
+ "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0"
+ [(set_attr "itanium_class" "fcvtfx")])
+
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
***************
*** 943,949 ****
(define_insn "fix_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
! ""
"fcvt.fx.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
--- 957,963 ----
(define_insn "fix_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fcvt.fx.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 951,957 ****
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
! ""
"fcvt.fx.trunc.s%2 %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
--- 965,971 ----
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
! "TARGET_80LD"
"fcvt.fx.trunc.s%2 %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 974,980 ****
(define_insn "floatunsditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
! ""
"fcvt.xuf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
--- 988,994 ----
(define_insn "floatunsditf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fcvt.xuf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 995,1001 ****
(define_insn "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
! ""
"fcvt.fxu.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
--- 1009,1015 ----
(define_insn "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
! "TARGET_80LD"
"fcvt.fxu.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 1003,1009 ****
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
! ""
"fcvt.fxu.trunc.s%2 %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
--- 1017,1023 ----
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
! "TARGET_80LD"
"fcvt.fxu.trunc.s%2 %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
***************
*** 1886,1892 ****
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
--- 1900,1906 ----
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
***************
*** 1925,1931 ****
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op2_neg, op1_di, div;
--- 1939,1945 ----
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op2_neg, op1_di, div;
***************
*** 1949,1955 ****
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
--- 1963,1969 ----
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
***************
*** 1988,1994 ****
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op2_neg, op1_di, div;
--- 2002,2008 ----
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op2_neg, op1_di, div;
***************
*** 2016,2022 ****
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
(use (match_operand:TF 3 "fr_register_operand" "f"))]
! "TARGET_INLINE_DIV"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2030,2036 ----
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
(use (match_operand:TF 3 "fr_register_operand" "f"))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2300,2306 ****
[(set (match_operand:DI 0 "register_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf;
--- 2314,2320 ----
[(set (match_operand:DI 0 "register_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf;
***************
*** 2330,2336 ****
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op2_neg, div;
--- 2344,2350 ----
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op2_neg, div;
***************
*** 2348,2354 ****
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf;
--- 2362,2368 ----
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op1_tf, op2_tf, op0_tf;
***************
*** 2378,2384 ****
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx op2_neg, div;
--- 2392,2398 ----
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx op2_neg, div;
***************
*** 2400,2406 ****
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2414,2420 ----
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2458,2464 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2472,2478 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2608,2614 ****
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx insn;
--- 2622,2628 ----
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx insn;
***************
*** 2627,2633 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 2641,2647 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 2681,2687 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 2695,2701 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 2912,2918 ****
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx insn;
--- 2926,2932 ----
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx insn;
***************
*** 2932,2938 ****
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
--- 2946,2952 ----
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
***************
*** 3009,3015 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 3023,3029 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 3075,3081 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fadd %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3089,3095 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fadd %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3084,3090 ****
(float_truncate:SF
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fadd.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3098,3104 ----
(float_truncate:SF
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fadd.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3093,3099 ****
(float_truncate:DF
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fadd.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3107,3113 ----
(float_truncate:DF
(plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fadd.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3101,3107 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fsub %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3115,3121 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fsub %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3110,3116 ****
(float_truncate:SF
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fsub.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3124,3130 ----
(float_truncate:SF
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fsub.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3119,3125 ****
(float_truncate:DF
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fsub.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3133,3139 ----
(float_truncate:DF
(minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fsub.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3127,3133 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fmpy %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3141,3147 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fmpy %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3136,3142 ****
(float_truncate:SF
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3150,3156 ----
(float_truncate:SF
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3145,3151 ****
(float_truncate:DF
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3159,3165 ----
(float_truncate:DF
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3154,3160 ****
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 3 "const_int_operand" ""))]
! ""
"fmpy.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3168,3174 ----
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 3 "const_int_operand" ""))]
! "TARGET_80LD"
"fmpy.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3164,3170 ****
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
! ""
"fmpy.s.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3178,3184 ----
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
! "TARGET_80LD"
"fmpy.s.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3174,3201 ****
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
! ""
"fmpy.d.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "abstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
! ""
"fabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negtf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
! ""
"fneg %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fnegabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
--- 3188,3215 ----
(mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
! "TARGET_80LD"
"fmpy.d.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "abstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negtf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fneg %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabstf2"
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fnegabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
***************
*** 3203,3209 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fmin %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
--- 3217,3223 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fmin %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
***************
*** 3211,3217 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! ""
"fmax %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
--- 3225,3231 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fmax %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
***************
*** 3220,3226 ****
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! ""
"fma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3234,3240 ----
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3230,3236 ****
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3244,3250 ----
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3240,3246 ****
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3254,3260 ----
(plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3250,3256 ****
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"fma.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3264,3270 ----
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"fma.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3261,3267 ****
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"fma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3275,3281 ----
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"fma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3270,3276 ****
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! ""
"fms %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3284,3290 ----
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fms %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3280,3286 ****
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3294,3300 ----
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3290,3296 ****
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fms.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3304,3310 ----
(minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fms.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3298,3304 ****
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fnmpy %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3312,3318 ----
[(set (match_operand:TF 0 "fr_register_operand" "=f")
(neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fnmpy %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3308,3314 ****
(neg:TF (mult:TF
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
! ""
"fnmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3322,3328 ----
(neg:TF (mult:TF
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
! "TARGET_80LD"
"fnmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3318,3324 ****
(neg:TF (mult:TF
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
! ""
"fnmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
--- 3332,3338 ----
(neg:TF (mult:TF
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
! "TARGET_80LD"
"fnmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
***************
*** 3330,3336 ****
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! ""
"fnma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3344,3350 ----
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
! "TARGET_80LD"
"fnma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3341,3347 ****
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3355,3361 ----
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3352,3358 ****
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! ""
"fnma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3366,3372 ----
(match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
! "TARGET_80LD"
"fnma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3363,3369 ****
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"fnma.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3377,3383 ----
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"fnma.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3376,3382 ****
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"fnma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
--- 3390,3396 ----
(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"fnma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
***************
*** 3384,3390 ****
[(set (match_operand:TF 0 "fr_register_operand" "")
(div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))]
! "TARGET_INLINE_DIV"
"
{
rtx insn;
--- 3398,3404 ----
[(set (match_operand:TF 0 "fr_register_operand" "")
(div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))]
! "TARGET_80LD && TARGET_INLINE_DIV"
"
{
rtx insn;
***************
*** 3405,3411 ****
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:TF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
! "TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 3419,3425 ----
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:TF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 3482,3488 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 3496,3502 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
! "TARGET_80LD && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 3562,3568 ****
(unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
(match_dup 3)] 5))
(use (match_operand:SI 4 "const_int_operand" ""))]
! ""
"frcpa.s%4 %0, %1 = %2, %3"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
--- 3576,3582 ----
(unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
(match_dup 3)] 5))
(use (match_operand:SI 4 "const_int_operand" ""))]
! "TARGET_80LD"
"frcpa.s%4 %0, %1 = %2, %3"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
***************
*** 3973,3979 ****
[(set (cc0)
(compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
(match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
! ""
"
{
ia64_compare_op0 = operands[0];
--- 3987,3993 ----
[(set (cc0)
(compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
(match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
! "TARGET_80LD"
"
{
ia64_compare_op0 = operands[0];
***************
*** 4046,4052 ****
(match_operator:BI 1 "comparison_operator"
[(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
! ""
"fcmp.%D1 %0, %I0 = %F2, %F3"
[(set_attr "itanium_class" "fcmp")])
--- 4060,4066 ----
(match_operator:BI 1 "comparison_operator"
[(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
(match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
! "TARGET_80LD"
"fcmp.%D1 %0, %I0 = %F2, %F3"
[(set_attr "itanium_class" "fcmp")])
*** config/ia64/t-hpux.orig Mon Mar 26 08:51:06 2001
--- config/ia64/t-hpux Fri Mar 23 13:51:58 2001
***************
*** 4,6 ****
--- 4,13 ----
# not defined in the test program.
LIBGCC1_TEST =
+
+ # Support routines for HP-UX 128 bit floats.
+
+ LIB2FUNCS_EXTRA=quadlib.c
+
+ quadlib.c: $(srcdir)/config/pa/quadlib.c
+ cat $(srcdir)/config/pa/quadlib.c > quadlib.c
*** config/ia64/hpux_longdouble.h.orig Mon Mar 26 08:51:45 2001
--- config/ia64/hpux_longdouble.h Fri Mar 23 10:01:20 2001
***************
*** 0 ****
--- 1,103 ----
+ /* Definitions of long double support for GNU compiler.
+ Copyright (C) 2000 Free Software Foundation, Inc.
+
+ This file is part of GNU CC.
+
+ GNU CC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GNU CC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GNU CC; see the file COPYING. If not, write to
+ the Free Software Foundation, 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+ /* Let subsequent headers know that we are not using
+ INTEL_EXTENDED_IEEE_FORMAT but true 128 bit floats. */
+
+ #define FULL_LONG_DOUBLE_FORMAT
+
+ /* Define library calls for quad FP operations. These are all part of the
+ IA32 and IA64 ABIs. */
+
+ #define ADDTF3_LIBCALL "_U_Qfadd"
+ #define SUBTF3_LIBCALL "_U_Qfsub"
+ #define MULTF3_LIBCALL "_U_Qfmpy"
+ #define DIVTF3_LIBCALL "_U_Qfdiv"
+ #define NEGTF2_LIBCALL "_U_Qfneg"
+ #define ABSTF2_LIBCALL "_U_Qfabs"
+ #define SMINTF3_LIBCALL "_U_Qfmin"
+ #define SMAXTF3_LIBCALL "_U_Qfmax"
+ #define EXTENDSFTF2_LIBCALL "_U_Qfcnvff_sgl_to_quad"
+ #define EXTENDDFTF2_LIBCALL "_U_Qfcnvff_dbl_to_quad"
+ #define TRUNCTFSF2_LIBCALL "_U_Qfcnvff_quad_to_sgl"
+ #define TRUNCTFDF2_LIBCALL "_U_Qfcnvff_quad_to_dbl"
+ #define FLOATSITF2_LIBCALL "_U_Qfcnvxf_sgl_to_quad"
+ #define FLOATDITF2_LIBCALL "_U_Qfcnvxf_dbl_to_quad"
+ #define FIX_TRUNCTFSI2_LIBCALL "_U_Qfcnvfxt_quad_to_sgl"
+ #define FIX_TRUNCTFDI2_LIBCALL "_U_Qfcnvfxt_quad_to_dbl"
+ #define EQTF2_LIBCALL "_U_Qfeq"
+ #define NETF2_LIBCALL "_U_Qfne"
+ #define GTTF2_LIBCALL "_U_Qfgt"
+ #define GETF2_LIBCALL "_U_Qfge"
+ #define LTTF2_LIBCALL "_U_Qflt"
+ #define LETF2_LIBCALL "_U_Qfle"
+
+
+ #undef INIT_TARGET_OPTABS
+ #define INIT_TARGET_OPTABS \
+ do { \
+ add_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, ADDTF3_LIBCALL); \
+ sub_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, SUBTF3_LIBCALL); \
+ smul_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, MULTF3_LIBCALL); \
+ flodiv_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, DIVTF3_LIBCALL); \
+ smin_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, SMINTF3_LIBCALL); \
+ smax_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, SMAXTF3_LIBCALL); \
+ abs_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, ABSTF2_LIBCALL); \
+ neg_optab->handlers[(int) TFmode].libfunc \
+ = gen_rtx_SYMBOL_REF (Pmode, NEGTF2_LIBCALL); \
+ extendsftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDSFTF2_LIBCALL); \
+ extenddftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDDFTF2_LIBCALL); \
+ trunctfsf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFSF2_LIBCALL); \
+ trunctfdf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFDF2_LIBCALL); \
+ floatsitf_libfunc = gen_rtx_SYMBOL_REF (Pmode, FLOATSITF2_LIBCALL); \
+ floatditf_libfunc = gen_rtx_SYMBOL_REF (Pmode, FLOATDITF2_LIBCALL); \
+ fixtfsi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFSI2_LIBCALL);\
+ fixtfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFDI2_LIBCALL);\
+ fixunstfsi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFSI2_LIBCALL); \
+ fixunstfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFDI2_LIBCALL); \
+ eqtf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EQTF2_LIBCALL); \
+ netf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, NETF2_LIBCALL); \
+ gttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GTTF2_LIBCALL); \
+ getf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GETF2_LIBCALL); \
+ lttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LTTF2_LIBCALL); \
+ letf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LETF2_LIBCALL); \
+ \
+ sdiv_optab->handlers[(int) SImode].libfunc = 0; \
+ udiv_optab->handlers[(int) SImode].libfunc = 0; \
+ smod_optab->handlers[(int) SImode].libfunc = 0; \
+ umod_optab->handlers[(int) SImode].libfunc = 0; \
+ \
+ INIT_SUBTARGET_OPTABS; \
+ } while (0)
+
+ /* This is meant to be redefined in the host dependent files */
+ #define INIT_SUBTARGET_OPTABS
+
+ /* Nonzero if a floating point comparison library call for
+ mode MODE that will return a boolean value. Zero if one
+ of the libgcc2 functions is used. */
+ #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
*** config/ia64/quadlib.c.orig Mon Mar 26 08:51:52 2001
--- config/ia64/quadlib.c Fri Mar 23 13:21:51 2001
***************
*** 0 ****
--- 1,82 ----
+ /* Subroutines for long double support.
+ Copyright (C) 2000 Free Software Foundation, Inc.
+
+ This file is part of GNU CC.
+
+ GNU CC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ In addition to the permissions in the GNU General Public License, the
+ Free Software Foundation gives you unlimited permission to link the
+ compiled version of this file into combinations with other programs,
+ and to distribute those combinations without any restriction coming
+ from the use of this file. (The General Public License restrictions
+ do apply in other respects; for example, they cover modification of
+ the file, and distribution when not linked into a combine
+ executable.)
+
+ GNU CC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GNU CC; see the file COPYING. If not, write to
+ the Free Software Foundation, 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+ int _U_Qfcmp (long double a, long double b, int);
+ long _U_Qfcnvfxt_quad_to_sgl (long double);
+
+ int
+ _U_Qfeq (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 4) != 0);
+ }
+
+ int
+ _U_Qfne (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 4) == 0);
+ }
+
+ int
+ _U_Qfgt (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 17) != 0);
+ }
+
+ int
+ _U_Qfge (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 21) != 0);
+ }
+
+ int
+ _U_Qflt (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 9) != 0);
+ }
+
+ int
+ _U_Qfle (long double a, long double b)
+ {
+ return (_U_Qfcmp (a, b, 13) != 0);
+ }
+
+ int
+ _U_Qfcomp (long double a, long double b)
+ {
+ if (_U_Qfcmp (a, b, 4) == 0)
+ return 0;
+
+ return (_U_Qfcmp (a, b, 22) != 0 ? 1 : -1);
+ }
+
+ long double
+ _U_Qfneg (long double a)
+ {
+ return (0.0L - a);
+ }