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X86_64 merger part 29 - conditional moves



Mon Mar 26 16:15:59 CEST 2001  Jan Hubicka  <jh@suse.cz>
	* i386.c (ix86_expand_setcc): Support 64bit.
	(ix86_expand_int_movcc): Likewise.
	* i386.md (movdicc_rex64, x86_movsicc_0_m1_rex64, movdicc_c_rex64):
	New patterns.
Index: i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.243
diff -c -3 -p -r1.243 i386.c
*** i386.c	2001/03/26 12:36:34	1.243
--- i386.c	2001/03/26 14:15:01
*************** ix86_expand_setcc (code, dest)
*** 6059,6065 ****
    rtx second_test, bypass_test;
    int type;
  
!   if (GET_MODE (ix86_compare_op0) == DImode)
      return 0; /* FAIL */
  
    /* Three modes of generation:
--- 6059,6066 ----
    rtx second_test, bypass_test;
    int type;
  
!   if (GET_MODE (ix86_compare_op0) == DImode
!       && !TARGET_64BIT)
      return 0; /* FAIL */
  
    /* Three modes of generation:
*************** ix86_expand_int_movcc (operands)
*** 6176,6181 ****
--- 6177,6183 ----
       HImode insns, we'd be swallowed in word prefix ops.  */
  
    if (GET_MODE (operands[0]) != HImode
+       && GET_MODE (operands[0]) != DImode
        && GET_CODE (operands[2]) == CONST_INT
        && GET_CODE (operands[3]) == CONST_INT)
      {
*************** ix86_expand_int_movcc (operands)
*** 6310,6336 ****
  
  	  nops = 0;
  	  if (diff == 1)
! 	      tmp = out;
  	  else
  	    {
! 	      tmp = gen_rtx_MULT (SImode, out, GEN_INT (diff & ~1));
  	      nops++;
  	      if (diff & 1)
  		{
! 		  tmp = gen_rtx_PLUS (SImode, tmp, out);
  		  nops++;
  		}
  	    }
  	  if (cf != 0)
  	    {
! 	      tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (cf));
  	      nops++;
  	    }
! 	  if (tmp != out)
  	    {
! 	      if (nops == 0)
! 		emit_move_insn (out, tmp);
! 	      else if (nops == 1)
  		{
  		  rtx clob;
  
--- 6312,6354 ----
  
  	  nops = 0;
  	  if (diff == 1)
! 	    {
! 	      if (Pmode != SImode)
! 		tmp = gen_lowpart (Pmode, out);
! 	      else
! 		tmp = out;
! 	    }
  	  else
  	    {
! 	      rtx out1;
! 	      if (Pmode != SImode)
! 	        out1 = gen_lowpart (Pmode, out);
! 	      else
! 		out1 = out;
! 	      tmp = gen_rtx_MULT (Pmode, out1, GEN_INT (diff & ~1));
  	      nops++;
  	      if (diff & 1)
  		{
! 		  tmp = gen_rtx_PLUS (Pmode, tmp, out1);
  		  nops++;
  		}
  	    }
  	  if (cf != 0)
  	    {
! 	      tmp = gen_rtx_PLUS (Pmode, tmp, GEN_INT (cf));
  	      nops++;
  	    }
! 	  if (tmp != out
! 	      && (GET_CODE (tmp) != SUBREG || SUBREG_REG (tmp) != out))
  	    {
! 	      if (Pmode != SImode)
! 	        tmp = gen_rtx_SUBREG (SImode, tmp, 0);
! 
! 	      /* ??? We should to take care for outputing non-lea arithmetics
! 	         for Pmode != SImode case too, but it is quite tricky and not
! 	         too important, since all TARGET_64BIT machines support real
! 	         conditional moves.  */
! 	      if (nops == 1 && Pmode == SImode)
  		{
  		  rtx clob;
  
Index: i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.249
diff -c -3 -p -r1.249 i386.md
*** i386.md	2001/03/26 13:56:34	1.249
--- i386.md	2001/03/26 14:15:11
***************
*** 14889,14894 ****
--- 14889,14932 ----
  
  ;; Conditional move instructions.
  
+ (define_expand "movdicc_rex64"
+   [(set (match_operand:DI 0 "register_operand" "")
+ 	(if_then_else:DI (match_operand 1 "comparison_operator" "")
+ 			 (match_operand:DI 2 "x86_64_general_operand" "")
+ 			 (match_operand:DI 3 "x86_64_general_operand" "")))]
+   "TARGET_64BIT"
+   "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+ 
+ (define_insn "x86_movsicc_0_m1_rex64"
+   [(set (match_operand:DI 0 "register_operand" "=r")
+ 	(if_then_else:DI (ltu (reg:CC 17) (const_int 0))
+ 	  (const_int -1)
+ 	  (const_int 0)))
+    (clobber (reg:CC 17))]
+   "TARGET_64BIT"
+   "sbb{l}\\t%0, %0"
+   ; Since we don't have the proper number of operands for an alu insn,
+   ; fill in all the blanks.
+   [(set_attr "type" "alu")
+    (set_attr "memory" "none")
+    (set_attr "imm_disp" "false")
+    (set_attr "mode" "DI")
+    (set_attr "length_immediate" "0")])
+ 
+ (define_insn "*movdicc_c_rex64"
+   [(set (match_operand:DI 0 "register_operand" "=r,r")
+ 	(if_then_else:DI (match_operator 1 "ix86_comparison_operator" 
+ 				[(reg 17) (const_int 0)])
+ 		      (match_operand:DI 2 "nonimmediate_operand" "rm,0")
+ 		      (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
+   "TARGET_64BIT && TARGET_CMOVE
+    && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
+   "@
+    cmov%C1\\t{%2, %0|%0, %2}
+    cmov%c1\\t{%3, %0|%0, %3}"
+   [(set_attr "type" "icmov")
+    (set_attr "mode" "DI")])
+ 
  (define_expand "movsicc"
    [(set (match_operand:SI 0 "register_operand" "")
  	(if_then_else:SI (match_operand 1 "comparison_operator" "")


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