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x86_64 merger part 26 - shift patterns
- To: rth at cygnus dot com, gcc-patches at gcc dot gnu dot org, patches at x86-64 dot org
- Subject: x86_64 merger part 26 - shift patterns
- From: Jan Hubicka <hubicka at atrey dot karlin dot mff dot cuni dot cz>
- Date: Sun, 25 Mar 2001 01:49:53 +0100
Ne bøe 25 01:24:07 CET 2001 Jan Hubicka <jh@suse.cz>
* (ashldi3_1_rex64, ashldi3_cmp_rex64, ashlsi3_1_zext, ashlsi3_cmp_zext,
ashrdi3_63_rex64, ashrdi3_1_one_bit_rex64, ashrdi3_1_rex64,
ashrdi3_one_bit_cmp_rex64, ashrdi3_cmp_rex64, ashrsi3_31_zext,
ashrsi3_1_one_bit_zext, ashrsi3_1_zext, ashrsi3_one_bit_cmp_zext,
ashrsi3_cmp_zext, lshrdi3_1_one_bit_rex64, lshrdi3_1_rex64,
lshrdi3_cmp_one_bit_rex64, lshrdi3_cmp_rex64, lshrsi3_1_one_bit_zext,
lshrsi3_1_zext, lshrsi3_cmp_one_bit_zext, lshrsi3_cmp_zext,
rotlsi3_1_one_bit_rex64, rotldi3_1_rex64,
rotlsi3_1_one_bit_zext, rotlsi3_1_zext, rotrdi3_1_one_bit_rex64,
rotrdi3_1_rex64, rotrsi3_1_one_bit_zext, rotrsi3_1_zext): New patterns.
(rotldi3, rotrdi3): New expanders.
*** ../2/i386.md Sun Mar 25 01:23:39 2001
--- i386.md Sun Mar 25 01:22:49 2001
***************
*** 8663,8668 ****
--- 8663,8773 ----
DONE;
}")
+ (define_insn "*ashldi3_1_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
+ (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
+ (match_operand:QI 2 "nonmemory_operand" "c,M")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
+ "*
+ {
+ switch (get_attr_type (insn))
+ {
+ case TYPE_ALU:
+ if (operands[2] != const1_rtx)
+ abort ();
+ if (!rtx_equal_p (operands[0], operands[1]))
+ abort ();
+ return \"add{q}\\t{%0, %0|%0, %0}\";
+
+ case TYPE_LEA:
+ if (GET_CODE (operands[2]) != CONST_INT
+ || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
+ abort ();
+ operands[1] = gen_rtx_MULT (DImode, operands[1],
+ GEN_INT (1 << INTVAL (operands[2])));
+ return \"lea{q}\\t{%a1, %0|%0, %a1}\";
+
+ default:
+ if (REG_P (operands[2]))
+ return \"sal{q}\\t{%b2, %0|%0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{q}\\t%0\";
+ else
+ return \"sal{q}\\t{%2, %0|%0, %2}\";
+ }
+ }"
+ [(set (attr "type")
+ (cond [(eq_attr "alternative" "1")
+ (const_string "lea")
+ (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
+ (const_int 0))
+ (match_operand 0 "register_operand" ""))
+ (match_operand 2 "const1_operand" ""))
+ (const_string "alu")
+ ]
+ (const_string "ishift")))
+ (set_attr "mode" "DI")])
+
+ ;; Convert lea to the lea pattern to avoid flags dependency.
+ (define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:QI 2 "immediate_operand" "")))
+ (clobber (reg:CC 17))]
+ "reload_completed
+ && TARGET_64BIT
+ && true_regnum (operands[0]) != true_regnum (operands[1])"
+ [(set (match_dup 0)
+ (mult:DI (match_dup 1)
+ (match_dup 2)))]
+ "operands[2] = GEN_INT (1 << INTVAL (operands[2]));")
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
+ (define_insn "*ashldi3_cmp_rex64"
+ [(set (reg 17)
+ (compare
+ (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "e"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (ashift:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
+ "*
+ {
+ switch (get_attr_type (insn))
+ {
+ case TYPE_ALU:
+ if (operands[2] != const1_rtx)
+ abort ();
+ return \"add{q}\\t{%0, %0|%0, %0}\";
+
+ default:
+ if (REG_P (operands[2]))
+ return \"sal{q}\\t{%b2, %0|%0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{q}\\t%0\";
+ else
+ return \"sal{q}\\t{%2, %0|%0, %2}\";
+ }
+ }"
+ [(set (attr "type")
+ (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
+ (const_int 0))
+ (match_operand 0 "register_operand" ""))
+ (match_operand 2 "const1_operand" ""))
+ (const_string "alu")
+ ]
+ (const_string "ishift")))
+ (set_attr "mode" "DI")])
+
(define_insn "ashldi3_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI (match_operand:DI 1 "register_operand" "0")
***************
*** 8837,8842 ****
--- 8942,9002 ----
DONE;
}")
+ (define_insn "*ashlsi3_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
+ (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
+ (clobber (reg:CC 17))]
+ "ix86_binary_operator_ok (ASHIFT, SImode, operands) && TARGET_64BIT"
+ "*
+ {
+ switch (get_attr_type (insn))
+ {
+ case TYPE_ALU:
+ if (operands[2] != const1_rtx)
+ abort ();
+ return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
+
+ case TYPE_LEA:
+ return \"#\";
+
+ default:
+ if (REG_P (operands[2]))
+ return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{l}\\t%k0\";
+ else
+ return \"sal{l}\\t{%2, %k0|%k0, %2}\";
+ }
+ }"
+ [(set (attr "type")
+ (cond [(eq_attr "alternative" "1")
+ (const_string "lea")
+ (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
+ (const_int 0))
+ (match_operand 2 "const1_operand" ""))
+ (const_string "alu")
+ ]
+ (const_string "ishift")))
+ (set_attr "mode" "SI")])
+
+ ;; Convert lea to the lea pattern to avoid flags dependency.
+ (define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
+ (match_operand:QI 2 "const_int_operand" ""))))
+ (clobber (reg:CC 17))]
+ "reload_completed
+ && true_regnum (operands[0]) != true_regnum (operands[1])"
+ [(set (match_dup 0) (zero_extend:DI (subreg:SI (mult:SI (match_dup 1) (match_dup 2)) 0)))]
+ "
+ {
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = GEN_INT (1 << INTVAL (operands[2]));
+ }")
+
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
***************
*** 8880,8885 ****
--- 9040,9084 ----
(const_string "ishift")))
(set_attr "mode" "SI")])
+ (define_insn "*ashlsi3_cmp_zext"
+ [(set (reg 17)
+ (compare
+ (ashift:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "I"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
+ "*
+ {
+ switch (get_attr_type (insn))
+ {
+ case TYPE_ALU:
+ if (operands[2] != const1_rtx)
+ abort ();
+ return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
+
+ default:
+ if (REG_P (operands[2]))
+ return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
+ else if (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 1
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
+ return \"sal{l}\\t%k0\";
+ else
+ return \"sal{l}\\t{%2, %k0|%k0, %2}\";
+ }
+ }"
+ [(set (attr "type")
+ (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
+ (const_int 0))
+ (match_operand 2 "const1_operand" ""))
+ (const_string "alu")
+ ]
+ (const_string "ishift")))
+ (set_attr "mode" "SI")])
+
(define_expand "ashlhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
***************
*** 9195,9200 ****
--- 9394,9480 ----
DONE;
}")
+ (define_insn "ashrdi3_63_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
+ (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
+ (match_operand:DI 2 "const_int_operand" "i,i")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
+ && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+ "@
+ {cqto|cqo}
+ sar{q}\\t{%2, %0|%0, %2}"
+ [(set_attr "type" "imovx,ishift")
+ (set_attr "prefix_0f" "0,*")
+ (set_attr "length_immediate" "0,*")
+ (set_attr "modrm" "0,1")
+ (set_attr "mode" "DI")])
+
+ (define_insn "*ashrdi3_1_one_bit_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "sar{q}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:DI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ (define_insn "*ashrdi3_1_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
+ (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
+ (match_operand:QI 2 "nonmemory_operand" "n,c")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+ "@
+ sar{q}\\t{%2, %0|%0, %2}
+ sar{q}\\t{%b2, %0|%0, %b2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "DI")])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
+ (define_insn "*ashrdi3_one_bit_cmp_rex64"
+ [(set (reg 17)
+ (compare
+ (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (ashiftrt:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+ "sar{q}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:DI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
+ (define_insn "*ashrdi3_cmp_rex64"
+ [(set (reg 17)
+ (compare
+ (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_operand" "n"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (ashiftrt:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+ "sar{q}\\t{%2, %0|%0, %2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "DI")])
+
+
(define_insn "ashrdi3_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
***************
*** 9295,9300 ****
--- 9575,9596 ----
(set_attr "modrm" "0,1")
(set_attr "mode" "SI")])
+ (define_insn "*ashrsi3_31_zext"
+ [(set (match_operand:DI 0 "register_operand" "=*d,r")
+ (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
+ (match_operand:SI 2 "const_int_operand" "i,i"))))
+ (clobber (reg:CC 17))]
+ "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
+ && TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+ "@
+ {cltd|cdqe}
+ sar{l}\\t{%2, %k0|%k0, %2}"
+ [(set_attr "type" "imovx,ishift")
+ (set_attr "prefix_0f" "0,*")
+ (set_attr "length_immediate" "0,*")
+ (set_attr "modrm" "0,1")
+ (set_attr "mode" "SI")])
+
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
***************
*** 9317,9322 ****
--- 9613,9629 ----
(const_string "2")
(const_string "*")))])
+ (define_insn "*ashrsi3_1_one_bit_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "sar{l}\\t%k0"
+ [(set_attr "type" "ishift")
+ (set_attr "length" "2")])
+
(define_insn "*ashrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
***************
*** 9329,9334 ****
--- 9636,9653 ----
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
+ (define_insn "*ashrsi3_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:QI 2 "nonmemory_operand" "I,c"))))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+ "@
+ sar{l}\\t{%2, %k0|%k0, %2}
+ sar{l}\\t{%b2, %k0|%k0, %b2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "SI")])
+
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
***************
*** 9350,9355 ****
--- 9669,9689 ----
(const_string "2")
(const_string "*")))])
+ (define_insn "*ashrsi3_one_bit_cmp_zext"
+ [(set (reg 17)
+ (compare
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+ "sar{l}\\t%k0"
+ [(set_attr "type" "ishift")
+ (set_attr "length" "2")])
+
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
***************
*** 9367,9372 ****
--- 9701,9720 ----
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
+ (define_insn "*ashrsi3_cmp_zext"
+ [(set (reg 17)
+ (compare
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "I"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+ "sar{l}\\t{%2, %k0|%k0, %2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "SI")])
+
(define_expand "ashrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
***************
*** 9532,9537 ****
--- 9880,9949 ----
DONE;
}")
+ (define_insn "*lshrdi3_1_one_bit_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "shr{q}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:DI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ (define_insn "*lshrdi3_1_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
+ (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
+ (match_operand:QI 2 "nonmemory_operand" "J,c")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+ "@
+ shr{q}\\t{%2, %0|%0, %2}
+ shr{q}\\t{%b2, %0|%0, %b2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "DI")])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
+ (define_insn "*lshrdi3_cmp_one_bit_rex64"
+ [(set (reg 17)
+ (compare
+ (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (lshiftrt:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+ "shr{q}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:DI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ ;; This pattern can't accept a variable shift count, since shifts by
+ ;; zero don't affect the flags. We assume that shifts by constant
+ ;; zero are optimized away.
+ (define_insn "*lshrdi3_cmp_rex64"
+ [(set (reg 17)
+ (compare
+ (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_operand" "e"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (lshiftrt:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+ "shr{q}\\t{%2, %0|%0, %2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "DI")])
+
(define_insn "lshrdi3_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
***************
*** 9592,9597 ****
--- 10004,10020 ----
(const_string "2")
(const_string "*")))])
+ (define_insn "*lshrsi3_1_one_bit_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "shr{l}\\t%k0"
+ [(set_attr "type" "ishift")
+ (set_attr "length" "2")])
+
(define_insn "*lshrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
***************
*** 9604,9609 ****
--- 10027,10045 ----
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
+ (define_insn "*lshrsi3_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI
+ (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
+ (match_operand:QI 2 "nonmemory_operand" "I,c"))))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+ "@
+ shr{l}\\t{%2, %k0|%k0, %2}
+ shr{l}\\t{%b2, %k0|%k0, %b2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "SI")])
+
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
***************
*** 9625,9630 ****
--- 10061,10081 ----
(const_string "2")
(const_string "*")))])
+ (define_insn "*lshrsi3_cmp_one_bit_zext"
+ [(set (reg 17)
+ (compare
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
+ && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+ "shr{l}\\t%k0"
+ [(set_attr "type" "ishift")
+ (set_attr "length" "2")])
+
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
***************
*** 9642,9647 ****
--- 10093,10112 ----
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
+ (define_insn "*lshrsi3_cmp_zext"
+ [(set (reg 17)
+ (compare
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "I"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+ "shr{l}\\t{%2, %k0|%k0, %2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "SI")])
+
(define_expand "lshrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
***************
*** 9788,9793 ****
--- 10253,10292 ----
;; Rotate instructions
+ (define_expand "rotldi3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT"
+ "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
+
+ (define_insn "*rotlsi3_1_one_bit_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "rol{q}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:DI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ (define_insn "*rotldi3_1_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
+ (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
+ (match_operand:QI 2 "nonmemory_operand" "e,c")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
+ "@
+ rol{q}\\t{%2, %0|%0, %2}
+ rol{q}\\t{%b2, %0|%0, %b2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "DI")])
+
(define_expand "rotlsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
***************
*** 9810,9815 ****
--- 10309,10326 ----
(const_string "2")
(const_string "*")))])
+ (define_insn "*rotlsi3_1_one_bit_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (rotate:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "rol{l}\\t%k0"
+ [(set_attr "type" "ishift")
+ (set_attr "length" "2")])
+
(define_insn "*rotlsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
***************
*** 9822,9827 ****
--- 10333,10351 ----
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
+ (define_insn "*rotlsi3_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI
+ (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:QI 2 "nonmemory_operand" "I,c"))))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
+ "@
+ rol{l}\\t{%2, %k0|%k0, %2}
+ rol{l}\\t{%b2, %k0|%k0, %b2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "SI")])
+
(define_expand "rotlhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
***************
*** 9890,9895 ****
--- 10414,10453 ----
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
+ (define_expand "rotrdi3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT"
+ "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
+
+ (define_insn "*rotrdi3_1_one_bit_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" "")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "ror{q}\\t%0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:DI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
+ (define_insn "*rotrdi3_1_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
+ (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
+ (match_operand:QI 2 "nonmemory_operand" "J,c")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
+ "@
+ ror{q}\\t{%2, %0|%0, %2}
+ ror{q}\\t{%b2, %0|%0, %b2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "DI")])
+
(define_expand "rotrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
***************
*** 9912,9917 ****
--- 10470,10490 ----
(const_string "2")
(const_string "*")))])
+ (define_insn "*rotrsi3_1_one_bit_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (rotatert:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "const_int_1_operand" ""))))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
+ && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
+ "ror{l}\\t%k0"
+ [(set_attr "type" "ishift")
+ (set (attr "length")
+ (if_then_else (match_operand:SI 0 "register_operand" "")
+ (const_string "2")
+ (const_string "*")))])
+
(define_insn "*rotrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
***************
*** 9921,9926 ****
--- 10494,10512 ----
"@
ror{l}\\t{%2, %0|%0, %2}
ror{l}\\t{%b2, %0|%0, %b2}"
+ [(set_attr "type" "ishift")
+ (set_attr "mode" "SI")])
+
+ (define_insn "*rotrsi3_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI
+ (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
+ (match_operand:QI 2 "nonmemory_operand" "I,c"))))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
+ "@
+ ror{l}\\t{%2, %k0|%k0, %2}
+ ror{l}\\t{%b2, %k0|%k0, %b2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])