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SSE scalar fp comparison patterns
- To: Richard Henderson <rth at redhat dot com>, gcc-patches at gcc dot gnu dot org, patches at x86-64 dot org
- Subject: SSE scalar fp comparison patterns
- From: Jan Hubicka <jh at suse dot cz>
- Date: Tue, 13 Feb 2001 10:27:03 +0100
Hi,
This patch adds SSE comparion instruction. Unlike the arithmetics
I allow mixed instructions even with not TARGET_MIX_I387_SSE.
This is consistent with my idea of keeping arithmetics exact, since
extra precisity won't hurt. On the other hand with current register
allocator implementation, gcc believes it can compare SSE regs with I387
making code bad. I will try to target the regclass problem instead of
disabling this feature at the moment - the code is ready, just need
updating.
Only conditional branches are supported at the moment. SSE has no direct
replacement for conditional moves I will implement later using logicals-on-FP
SSE feature.
Honza
Tue Feb 13 10:16:50 CET 2001 Jan Hubicka <jh@suse.cz>
* i386.c (output_fp_compare): Support SSE.
(prepare_fp_compare_args): SSE comparisons always support memory.
* i386.h (TARGET_CMOVE): SSE imply cmove.
* i386.md (cmp?f2): Enable for SSE too.
(cmpfp_i*): Support SSE.
(cmpfp_i_sse): New.
(cmpfp_i_sse_only): New.
(s*, b* fp expanters): Enable for SSE too.
(fp_jcc_1_sse, fp_jcc_1_sse_only, fp_jcc_2_sse, fp_jcc_2_sse_only):
New patterns.
Index: i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.211
diff -c -3 -p -r1.211 i386.c
*** i386.c 2001/02/08 19:15:37 1.211
--- i386.c 2001/02/13 09:10:32
*************** output_fp_compare (insn, operands, eflag
*** 4021,4032 ****
--- 4043,4068 ----
int stack_top_dies;
rtx cmp_op0 = operands[0];
rtx cmp_op1 = operands[1];
+ int is_sse = SSE_REG_P (operands[0]) | SSE_REG_P (operands[1]);
if (eflags_p == 2)
{
cmp_op0 = cmp_op1;
cmp_op1 = operands[2];
}
+ if (is_sse)
+ {
+ if (GET_MODE (operands[0]) == SFmode)
+ if (unordered_p)
+ return "ucomiss\t{%1, %0|%0, %1}";
+ else
+ return "comiss\t{%1, %0|%0, %y}";
+ else
+ if (unordered_p)
+ return "ucomisd\t{%1, %0|%0, %1}";
+ else
+ return "comisd\t{%1, %0|%0, %y}";
+ }
if (! STACK_TOP_P (cmp_op0))
abort ();
*************** ix86_prepare_fp_compare_args (code, pop0
*** 4782,4796 ****
enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
rtx op0 = *pop0, op1 = *pop1;
enum machine_mode op_mode = GET_MODE (op0);
/* All of the unordered compare instructions only work on registers.
The same is true of the XFmode compare instructions. The same is
true of the fcomi compare instructions. */
! if (fpcmp_mode == CCFPUmode
! || op_mode == XFmode
! || op_mode == TFmode
! || ix86_use_fcomi_compare (code))
{
op0 = force_reg (op_mode, op0);
op1 = force_reg (op_mode, op1);
--- 4818,4834 ----
enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
rtx op0 = *pop0, op1 = *pop1;
enum machine_mode op_mode = GET_MODE (op0);
+ int is_sse = SSE_REG_P (op0) | SSE_REG_P (op1);
/* All of the unordered compare instructions only work on registers.
The same is true of the XFmode compare instructions. The same is
true of the fcomi compare instructions. */
! if (!is_sse
! && (fpcmp_mode == CCFPUmode
! || op_mode == XFmode
! || op_mode == TFmode
! || ix86_use_fcomi_compare (code)))
{
op0 = force_reg (op_mode, op0);
op1 = force_reg (op_mode, op1);
Index: i386.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.h,v
retrieving revision 1.147
diff -c -3 -p -r1.147 i386.h
*** i386.h 2001/02/08 19:15:37 1.147
--- i386.h 2001/02/13 09:10:50
*************** extern const int x86_partial_reg_depende
*** 192,198 ****
#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
#define TARGET_USE_Q_REG (x86_use_q_reg & CPUMASK)
#define TARGET_USE_ANY_REG (x86_use_any_reg & CPUMASK)
! #define TARGET_CMOVE (x86_cmove & (1 << ix86_arch))
#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
#define TARGET_USE_SAHF (x86_use_sahf & CPUMASK)
--- 194,202 ----
#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
#define TARGET_USE_Q_REG (x86_use_q_reg & CPUMASK)
#define TARGET_USE_ANY_REG (x86_use_any_reg & CPUMASK)
! /* For sane SSE instruction set generation we need fcomi instruction. It is
! safe to enable all CMOVE instructions. */
! #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
#define TARGET_USE_SAHF (x86_use_sahf & CPUMASK)
Index: i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.204
diff -c -3 -p -r1.204 i386.md
*** i386.md 2001/01/29 18:31:35 1.204
--- i386.md 2001/02/13 09:11:56
***************
*** 1268,1274 ****
[(set (reg:CC 17)
(compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
(match_operand:DF 1 "cmp_fp_expander_operand" "")))]
! "TARGET_80387"
"
{
ix86_compare_op0 = operands[0];
--- 1268,1274 ----
[(set (reg:CC 17)
(compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
(match_operand:DF 1 "cmp_fp_expander_operand" "")))]
! "TARGET_80387 || TARGET_SSE2"
"
{
ix86_compare_op0 = operands[0];
***************
*** 1280,1286 ****
[(set (reg:CC 17)
(compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
(match_operand:SF 1 "cmp_fp_expander_operand" "")))]
! "TARGET_80387"
"
{
ix86_compare_op0 = operands[0];
--- 1280,1286 ----
[(set (reg:CC 17)
(compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
(match_operand:SF 1 "cmp_fp_expander_operand" "")))]
! "TARGET_80387 || TARGET_SSE"
"
{
ix86_compare_op0 = operands[0];
***************
*** 1504,1509 ****
--- 1504,1510 ----
(compare:CCFP (match_operand 0 "register_operand" "f")
(match_operand 1 "register_operand" "f")))]
"TARGET_80387 && TARGET_CMOVE
+ && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
***************
*** 1511,1527 ****
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
(define_insn "*cmpfp_iu"
[(set (reg:CCFPU 17)
(compare:CCFPU (match_operand 0 "register_operand" "f")
(match_operand 1 "register_operand" "f")))]
"TARGET_80387 && TARGET_CMOVE
&& FLOAT_MODE_P (GET_MODE (operands[0]))
! && GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
[(set_attr "type" "fcmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
;; Move instructions.
--- 1512,1575 ----
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
+ (define_insn "*cmpfp_i_sse"
+ [(set (reg:CCFP 17)
+ (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
+ (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
+ "TARGET_80387
+ && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && GET_MODE (operands[0]) == GET_MODE (operands[0])"
+ "* return output_fp_compare (insn, operands, 1, 0);"
+ [(set_attr "type" "fcmp,sse")
+ (set_attr "mode" "unknownfp")
+ (set_attr "athlon_decode" "vector")])
+
+ (define_insn "*cmpfp_i_sse_only"
+ [(set (reg:CCFP 17)
+ (compare:CCFP (match_operand 0 "register_operand" "x")
+ (match_operand 1 "nonimmediate_operand" "xm")))]
+ "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && GET_MODE (operands[0]) == GET_MODE (operands[0])"
+ "* return output_fp_compare (insn, operands, 1, 0);"
+ [(set_attr "type" "sse")
+ (set_attr "mode" "unknownfp")
+ (set_attr "athlon_decode" "vector")])
+
(define_insn "*cmpfp_iu"
[(set (reg:CCFPU 17)
(compare:CCFPU (match_operand 0 "register_operand" "f")
(match_operand 1 "register_operand" "f")))]
"TARGET_80387 && TARGET_CMOVE
+ && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& FLOAT_MODE_P (GET_MODE (operands[0]))
! && GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 1);"
[(set_attr "type" "fcmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
+
+ (define_insn "*cmpfp_iu_sse"
+ [(set (reg:CCFPU 17)
+ (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
+ (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
+ "TARGET_80387
+ && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])"
+ "* return output_fp_compare (insn, operands, 1, 1);"
+ [(set_attr "type" "fcmp,sse")
+ (set_attr "mode" "unknownfp")
+ (set_attr "athlon_decode" "vector")])
+
+ (define_insn "*cmpfp_iu_sse_only"
+ [(set (reg:CCFPU 17)
+ (compare:CCFPU (match_operand 0 "register_operand" "x")
+ (match_operand 1 "nonimmediate_operand" "xm")))]
+ "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])"
+ "* return output_fp_compare (insn, operands, 1, 1);"
+ [(set_attr "type" "sse")
+ (set_attr "mode" "unknownfp")
+ (set_attr "athlon_decode" "vector")])
;; Move instructions.
***************
*** 9006,9012 ****
(define_expand "sunordered"
[(set (match_operand:SI 0 "register_operand" "")
(unordered:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387"
"if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
(define_expand "sordered"
--- 9250,9256 ----
(define_expand "sunordered"
[(set (match_operand:SI 0 "register_operand" "")
(unordered:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
(define_expand "sordered"
***************
*** 9018,9054 ****
(define_expand "suneq"
[(set (match_operand:SI 0 "register_operand" "")
(uneq:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387"
"if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
(define_expand "sunge"
[(set (match_operand:SI 0 "register_operand" "")
(unge:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387"
"if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
(define_expand "sungt"
[(set (match_operand:SI 0 "register_operand" "")
(ungt:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387"
"if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
(define_expand "sunle"
[(set (match_operand:SI 0 "register_operand" "")
(unle:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387"
"if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
(define_expand "sunlt"
[(set (match_operand:SI 0 "register_operand" "")
(unlt:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387"
"if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
(define_expand "sltgt"
[(set (match_operand:SI 0 "register_operand" "")
(ltgt:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387"
"if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
(define_insn "*setcc_1"
--- 9262,9298 ----
(define_expand "suneq"
[(set (match_operand:SI 0 "register_operand" "")
(uneq:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
(define_expand "sunge"
[(set (match_operand:SI 0 "register_operand" "")
(unge:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
(define_expand "sungt"
[(set (match_operand:SI 0 "register_operand" "")
(ungt:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
(define_expand "sunle"
[(set (match_operand:SI 0 "register_operand" "")
(unle:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
(define_expand "sunlt"
[(set (match_operand:SI 0 "register_operand" "")
(unlt:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
(define_expand "sltgt"
[(set (match_operand:SI 0 "register_operand" "")
(ltgt:SI (reg:CC 17) (const_int 0)))]
! "TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
(define_insn "*setcc_1"
***************
*** 9161,9167 ****
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387"
"ix86_expand_branch (UNORDERED, operands[0]); DONE;")
(define_expand "bordered"
--- 9405,9411 ----
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387 || TARGET_SSE"
"ix86_expand_branch (UNORDERED, operands[0]); DONE;")
(define_expand "bordered"
***************
*** 9169,9175 ****
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387"
"ix86_expand_branch (ORDERED, operands[0]); DONE;")
(define_expand "buneq"
--- 9413,9419 ----
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387 || TARGET_SSE"
"ix86_expand_branch (ORDERED, operands[0]); DONE;")
(define_expand "buneq"
***************
*** 9177,9183 ****
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387"
"ix86_expand_branch (UNEQ, operands[0]); DONE;")
(define_expand "bunge"
--- 9421,9427 ----
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387 || TARGET_SSE"
"ix86_expand_branch (UNEQ, operands[0]); DONE;")
(define_expand "bunge"
***************
*** 9185,9191 ****
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387"
"ix86_expand_branch (UNGE, operands[0]); DONE;")
(define_expand "bungt"
--- 9429,9435 ----
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387 || TARGET_SSE"
"ix86_expand_branch (UNGE, operands[0]); DONE;")
(define_expand "bungt"
***************
*** 9193,9199 ****
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387"
"ix86_expand_branch (UNGT, operands[0]); DONE;")
(define_expand "bunle"
--- 9437,9443 ----
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387 || TARGET_SSE"
"ix86_expand_branch (UNGT, operands[0]); DONE;")
(define_expand "bunle"
***************
*** 9201,9207 ****
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387"
"ix86_expand_branch (UNLE, operands[0]); DONE;")
(define_expand "bunlt"
--- 9445,9451 ----
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387 || TARGET_SSE"
"ix86_expand_branch (UNLE, operands[0]); DONE;")
(define_expand "bunlt"
***************
*** 9209,9215 ****
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387"
"ix86_expand_branch (UNLT, operands[0]); DONE;")
(define_expand "bltgt"
--- 9453,9459 ----
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387 || TARGET_SSE"
"ix86_expand_branch (UNLT, operands[0]); DONE;")
(define_expand "bltgt"
***************
*** 9217,9223 ****
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387"
"ix86_expand_branch (LTGT, operands[0]); DONE;")
(define_insn "*jcc_1"
--- 9461,9467 ----
(if_then_else (match_dup 1)
(label_ref (match_operand 0 "" ""))
(pc)))]
! "TARGET_80387 || TARGET_SSE"
"ix86_expand_branch (LTGT, operands[0]); DONE;")
(define_insn "*jcc_1"
***************
*** 9268,9277 ****
--- 9512,9549 ----
(clobber (reg:CCFP 18))
(clobber (reg:CCFP 17))]
"TARGET_CMOVE && TARGET_80387
+ && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
"#")
+ (define_insn "*fp_jcc_1_sse"
+ [(set (pc)
+ (if_then_else (match_operator 0 "comparison_operator"
+ [(match_operand 1 "register_operand" "f#x,x#f")
+ (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CCFP 18))
+ (clobber (reg:CCFP 17))]
+ "TARGET_80387
+ && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
+ && GET_MODE (operands[1]) == GET_MODE (operands[2])"
+ "#")
+
+ (define_insn "*fp_jcc_1_sse_only"
+ [(set (pc)
+ (if_then_else (match_operator 0 "comparison_operator"
+ [(match_operand 1 "register_operand" "f#x,x#f")
+ (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CCFP 18))
+ (clobber (reg:CCFP 17))]
+ "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
+ && GET_MODE (operands[1]) == GET_MODE (operands[2])"
+ "#")
+
(define_insn "*fp_jcc_2"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
***************
*** 9282,9291 ****
--- 9554,9578 ----
(clobber (reg:CCFP 18))
(clobber (reg:CCFP 17))]
"TARGET_CMOVE && TARGET_80387
+ && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
"#")
+ (define_insn "*fp_jcc_2_sse"
+ [(set (pc)
+ (if_then_else (match_operator 0 "comparison_operator"
+ [(match_operand 1 "register_operand" "f#x,x#f")
+ (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
+ (pc)
+ (label_ref (match_operand 3 "" ""))))
+ (clobber (reg:CCFP 18))
+ (clobber (reg:CCFP 17))]
+ "TARGET_80387
+ && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
+ && GET_MODE (operands[1]) == GET_MODE (operands[2])"
+ "#")
+
(define_insn "*fp_jcc_3"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"