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[PATCH]: Fix constraints in 68HC11/HC12 port
- To: gcc-patches at gcc dot gnu dot org
- Subject: [PATCH]: Fix constraints in 68HC11/HC12 port
- From: Stephane Carrez <Stephane dot Carrez at worldnet dot fr>
- Date: Thu, 11 Jan 2001 22:16:27 +0100
Hi!
With HC11/HC12 port, it sometimes happen that Gcc tries to reload
an operand in a register of class S_REGS (constraint 'u'). These
registers are the soft registers, mapped in memory. When such
register is picked for reload, this is the big *catastrophe*
because the movM pattern is not able to move the operand to/from
the S_REGS register because it would require a hard register
as temporary, ie a scratch (there is no memory <-> memory move).
By putting the 'm' constraint before the 'u' constraint, or
splitting the "mu" constraint to "m,u", the reload is avoided.
The movstrictqi has a reload problem with D_REGS which only contains
1 register. It reloading occurs, ..., no way this is a spill failure.
By fixing and disparaging severly the alternative, reloading does not
occur.
I've integrated the patch below to fix these constraints problems.
Stephane
2001-01-11 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* config/m68hc11/m68hc11.md (cmphi_1): Make sure reloading
in S_REGS does not occur because not all sources are possible
when a S_REGS is a destination (sometimes needs a clobber).
(movqi_const0, zero_extendhisi2, zero_extendqisi2): Likewise.
(zero_extendhidi2, extendqisi2, extendqihi2, extendhisi2): Likewise.
(anddi3, iordi3, xordi3, negqi2, one_cmplhi2, one_cmplqi2: Likewise.
(ashldi3_const32, ashldi3_const1, ashlsi3_const16): Likewise.
(ashlsi3_const1, ashlhi3_2, ashlqi3_const1, ashrhi3): Likewise.
(ashrqi3_const1, lshrdi3_const32, lshrdi3_const63): Likewise.
(lshrdi_const1, lshrsi3_const16): Likewise.
(*addhi3, lshrsi3_const1, lshrqi3_const1): Likewise.
(*movhi_68hc12, *movqi_68hc12): Likewise.
(movstrictqi): Make sure reloading in D_REGS as a destination
does not happen.
Index: m68hc11.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/m68hc11/m68hc11.md,v
retrieving revision 1.2
diff -u -r1.2 m68hc11.md
--- m68hc11.md 2001/01/11 21:10:39 1.2
+++ m68hc11.md 2001/01/11 21:24:42
@@ -285,9 +285,9 @@
(define_insn "cmphi_1"
[(set (cc0)
(compare (match_operand:HI 0 "tst_operand"
- "dxy,?xy,d,dxy,dxy,dxy")
+ "xy,d,?xy,d,dxy,dxy,dxy")
(match_operand:HI 1 "cmp_operand"
- "i,m,m,?*d*A,?u,!*w")))]
+ "i,i,m,m,?*d*A,?u,!*w")))]
""
"*
{
@@ -458,8 +458,8 @@
"")
(define_insn "movstrictqi"
- [(set (strict_low_part (match_operand:QI 0 "non_push_operand" "+mu,+d,+d"))
- (match_operand:QI 1 "general_operand" "d,dim,u"))]
+ [(set (strict_low_part (match_operand:QI 0 "non_push_operand" "+mu,+!d"))
+ (match_operand:QI 1 "general_operand" "d,imu"))]
""
"#")
@@ -652,8 +652,8 @@
clr\\t%b0\\n\\tclr\\t%h0")
(define_insn "*movhi_68hc12"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=dAwuU,dAwu,m")
- (match_operand:HI 1 "general_operand" "ruUi,m,dAwu"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=U,dAw,U,U,m,!u")
+ (match_operand:HI 1 "general_operand" "U,rim,dAwi,!u,dAw,riU"))]
"TARGET_M6812"
"*
{
@@ -680,12 +680,13 @@
;; This should be ok since this is not the (strict_low_part) set.
;;
(define_insn "movqi_const0"
- [(set (match_operand:QI 0 "non_push_operand" "=d,!um,*A,!*q")
+ [(set (match_operand:QI 0 "non_push_operand" "=d,m,!u,*A,!*q")
(const_int 0))]
""
"@
clrb
clr\\t%b0
+ clr\\t%b0
ld%0\\t#0
clr%0")
@@ -769,7 +770,7 @@
}")
(define_insn "*movqi_68hc12"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d*AuU*q,d*A*q,d*A*q,m,m")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d*AuU*q,d*A*qu,d*A*q,m,m")
(match_operand:QI 1 "general_operand" "rui*q,U,m,d*q,!A"))]
"TARGET_M6812"
"*
@@ -841,7 +842,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,!u,m,!u")
(zero_extend:DI
(match_operand:QI 1 "nonimmediate_operand" "m,dmu,*B,*B")))
- (clobber (match_scratch:HI 2 "=&d,&dB,&dB,&dB"))]
+ (clobber (match_scratch:HI 2 "=&d,&dB,&d,&dB"))]
""
"#")
@@ -935,10 +936,10 @@
}")
(define_insn "zero_extendhidi2"
- [(set (match_operand:DI 0 "non_push_operand" "=m,m,m,!u,!u")
+ [(set (match_operand:DI 0 "non_push_operand" "=m,m,m,m,!u,!u")
(zero_extend:DI
- (match_operand:HI 1 "nonimmediate_operand" "m,dA,!u,dmA,!u")))
- (clobber (match_scratch:HI 2 "=&d,&dB,&dB,&dB,&dB"))]
+ (match_operand:HI 1 "nonimmediate_operand" "m,d,A,!u,dmA,!u")))
+ (clobber (match_scratch:HI 2 "=&d,&B,&d,&dB,&dB,&dB"))]
""
"#")
@@ -1008,10 +1009,10 @@
;; because it's less efficient.
;;
(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "non_push_operand" "=D,mu,m,m,!u,!u")
+ [(set (match_operand:SI 0 "non_push_operand" "=D,m,u,m,m,!u,!u")
(zero_extend:SI
- (match_operand:HI 1 "nonimmediate_operand" "dAmu,dA,m,!u,m,!u")))
- (clobber (match_scratch:HI 2 "=X,X,&d,&dB,&dB,&dB"))]
+ (match_operand:HI 1 "nonimmediate_operand" "dAmu,dA,dA,m,!u,m,!u")))
+ (clobber (match_scratch:HI 2 "=X,X,X,&d,&dB,&dB,&dB"))]
""
"#")
@@ -1037,9 +1038,9 @@
}")
(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "non_push_operand" "=D,mu")
+ [(set (match_operand:SI 0 "non_push_operand" "=D,m,u")
(zero_extend:SI
- (match_operand:QI 1 "nonimmediate_operand" "dxymu,dxy")))]
+ (match_operand:QI 1 "nonimmediate_operand" "dxymu,dxy,dxy")))]
""
"#")
@@ -1168,8 +1169,8 @@
;;--------------------------------------------------------------------
(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=D,mu")
- (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "dmux,d")))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=D,m,u")
+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "dmux,d,d")))]
""
"*
{
@@ -1259,8 +1260,8 @@
(define_insn "extendqihi2"
- [(set (match_operand:HI 0 "non_push_operand" "=d,u*x*ym")
- (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "dum,0")))]
+ [(set (match_operand:HI 0 "non_push_operand" "=d,*x*ym,u")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "dum,0,0")))]
""
"*
{
@@ -1921,7 +1922,7 @@
"")
(define_insn "*addhi3"
- [(set (match_operand:HI 0 "hard_reg_operand" "=dA,d,!A,d*A,!d,!w")
+ [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d,!w")
(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0,0")
(match_operand:HI 2 "general_operand" "N,i,I,umi*A*d,!*d*w,i")))]
"TARGET_M6811"
@@ -2555,10 +2556,10 @@
;;--------------------------------------------------------------------
(define_insn "anddi3"
- [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=mu")
- (and:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu")
- (match_operand:DI 2 "general_operand" "imu")))
- (clobber (match_scratch:HI 3 "=d"))]
+ [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
+ (and:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
+ (match_operand:DI 2 "general_operand" "imu,imu")))
+ (clobber (match_scratch:HI 3 "=d,d"))]
""
"#")
@@ -2709,10 +2710,10 @@
;;--------------------------------------------------------------------
(define_insn "iordi3"
- [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=mu")
- (ior:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu")
- (match_operand:DI 2 "general_operand" "imu")))
- (clobber (match_scratch:HI 3 "=d"))]
+ [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
+ (ior:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
+ (match_operand:DI 2 "general_operand" "imu,imu")))
+ (clobber (match_scratch:HI 3 "=d,d"))]
""
"#")
@@ -2803,10 +2804,10 @@
;;--------------------------------------------------------------------
(define_insn "xordi3"
- [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=mu")
- (xor:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu")
- (match_operand:DI 2 "general_operand" "imu")))
- (clobber (match_scratch:HI 3 "=d"))]
+ [(set (match_operand:DI 0 "reg_or_some_mem_operand" "=m,u")
+ (xor:DI (match_operand:DI 1 "reg_or_some_mem_operand" "%imu,imu")
+ (match_operand:DI 2 "general_operand" "imu,imu")))
+ (clobber (match_scratch:HI 3 "=d,d"))]
""
"#")
@@ -3478,12 +3479,13 @@
xgd%0\\n\\tcoma\\n\\tcomb\\n\\txgd%0\\n\\tin%0")
(define_insn "negqi2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!um,!*A")
- (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0")))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m,!u,!*A")
+ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0")))]
""
"@
negb
neg\\t%b0
+ neg\\t%b0
#")
;;
@@ -3504,21 +3506,23 @@
"bsr\\t___one_cmplsi2")
(define_insn "one_cmplhi2"
- [(set (match_operand:HI 0 "non_push_operand" "=d,!um,*A")
- (not:HI (match_operand:HI 1 "general_operand" "0,0,0")))]
+ [(set (match_operand:HI 0 "non_push_operand" "=d,m,!u,*A")
+ (not:HI (match_operand:HI 1 "general_operand" "0,0,0,0")))]
""
"@
comb\\n\\tcoma
com\\t%b0\\n\\tcom\\t%h0
+ com\\t%b0\\n\\tcom\\t%h0
#")
(define_insn "one_cmplqi2"
- [(set (match_operand:QI 0 "non_push_operand" "=d,!um,!*A")
- (not:QI (match_operand:QI 1 "general_operand" "0,0,0")))]
+ [(set (match_operand:QI 0 "non_push_operand" "=d,m,!u,!*A")
+ (not:QI (match_operand:QI 1 "general_operand" "0,0,0,0")))]
""
"@
comb
com\\t%b0
+ com\\t%b0
#")
(define_split /* "*one_cmplsi2" */
@@ -3569,10 +3573,10 @@
}")
(define_insn "*ashldi3_const32"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=<,um")
- (ashift:DI (match_operand:DI 1 "general_operand" "umi,umi")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=<,m,u")
+ (ashift:DI (match_operand:DI 1 "general_operand" "umi,umi,umi")
(const_int 32)))
- (clobber (match_scratch:HI 2 "=A,d"))]
+ (clobber (match_scratch:HI 2 "=A,d,d"))]
""
"#")
@@ -3601,10 +3605,10 @@
DONE;")
(define_insn "*ashldi3_const1"
- [(set (match_operand:DI 0 "non_push_operand" "=um")
- (ashift:DI (match_operand:DI 1 "general_operand" "umi")
+ [(set (match_operand:DI 0 "non_push_operand" "=m,m,u")
+ (ashift:DI (match_operand:DI 1 "general_operand" "mi,u,umi")
(const_int 1)))
- (clobber (match_scratch:HI 2 "=d"))]
+ (clobber (match_scratch:HI 2 "=d,d,d"))]
""
"#")
@@ -3739,10 +3743,10 @@
operands[3] = m68hc11_gen_lowpart (HImode, operands[1]);")
(define_insn "*ashlsi3_const16"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=D,*um")
- (ashift:SI (match_operand:SI 1 "general_operand" "Duim,D")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=D,m,*u")
+ (ashift:SI (match_operand:SI 1 "general_operand" "Duim,D,D")
(const_int 16)))
- (clobber (match_scratch:HI 2 "=X,X"))]
+ (clobber (match_scratch:HI 2 "=X,X,X"))]
""
"#")
@@ -3767,10 +3771,10 @@
"")
(define_insn "*ashlsi3_const1"
- [(set (match_operand:SI 0 "non_push_operand" "=D,D,*um,?*um")
- (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,*um,0,*um")
+ [(set (match_operand:SI 0 "non_push_operand" "=D,D,m,!*u,?*um")
+ (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,*um,0,0,*um")
(const_int 1)))
- (clobber (match_scratch:HI 2 "=X,X,&d,&d"))]
+ (clobber (match_scratch:HI 2 "=X,X,&d,&d,&d"))]
""
"*
{
@@ -3973,13 +3977,14 @@
"")
(define_insn "*ashlqi3_const1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!um,!*q,!*A")
- (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m,!u,!*q,!*A")
+ (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0,0")
(const_int 1)))]
""
"@
aslb
asl\\t%b0
+ asl\\t%b0
asl%0
#")
@@ -4268,13 +4273,14 @@
"")
(define_insn "*ashrqi3_const1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!um,!*q,!*A")
- (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m,!u,!*q,!*A")
+ (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0,0")
(const_int 1)))]
""
"@
asrb
asr\\t%b0
+ asr\\t%b0
asr%0
#")
@@ -4346,10 +4352,10 @@
}")
(define_insn "*lshrdi3_const32"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=<,um")
- (lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=<,m,u")
+ (lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi,umi")
(const_int 32)))
- (clobber (match_scratch:HI 2 "=A,d"))]
+ (clobber (match_scratch:HI 2 "=A,d,d"))]
""
"#")
@@ -4368,10 +4374,10 @@
DONE;")
(define_insn "*lshrdi3_const63"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=um")
- (lshiftrt:DI (match_operand:DI 1 "general_operand" "umi")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,u")
+ (lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi")
(match_operand:DI 2 "const_int_operand" "")))
- (clobber (match_scratch:HI 3 "=d"))]
+ (clobber (match_scratch:HI 3 "=d,d"))]
"INTVAL (operands[2]) >= 48"
"#")
@@ -4428,10 +4434,10 @@
operands[6] = m68hc11_gen_lowpart (HImode, operands[6]);")
(define_insn "*lshrdi_const1"
- [(set (match_operand:DI 0 "non_push_operand" "=um")
- (lshiftrt:DI (match_operand:DI 1 "general_operand" "umi")
+ [(set (match_operand:DI 0 "non_push_operand" "=m,u")
+ (lshiftrt:DI (match_operand:DI 1 "general_operand" "umi,umi")
(const_int 1)))
- (clobber (match_scratch:HI 2 "=d"))]
+ (clobber (match_scratch:HI 2 "=d,d"))]
""
"#")
@@ -4497,20 +4503,20 @@
operands[3] = m68hc11_gen_highpart (HImode, operands[1]);")
(define_insn "*lshrsi3_const16"
- [(set (match_operand:SI 0 "non_push_operand" "=D,D,um")
- (lshiftrt:SI (match_operand:SI 1 "general_operand" "uim,0,D")
+ [(set (match_operand:SI 0 "non_push_operand" "=D,D,m,u")
+ (lshiftrt:SI (match_operand:SI 1 "general_operand" "uim,0,D,D")
(const_int 16)))
- (clobber (match_scratch:HI 2 "=X,X,X"))]
+ (clobber (match_scratch:HI 2 "=X,X,X,X"))]
""
"#
xgdx\\n\\tldx\\t#0
#")
(define_insn "*lshrsi3_const1"
- [(set (match_operand:SI 0 "non_push_operand" "=D,*um")
- (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "D*um,*um")
+ [(set (match_operand:SI 0 "non_push_operand" "=D,m,*u")
+ (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "D*um,*um,*um")
(const_int 1)))
- (clobber (match_scratch:HI 2 "=X,&d"))]
+ (clobber (match_scratch:HI 2 "=X,&d,&d"))]
""
"*
{
@@ -4745,12 +4751,13 @@
"")
(define_insn "*lshrqi3_const1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!um,!*q,!*A")
- (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m,!u,!*q,!*A")
+ (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,0,0,0")
(const_int 1)))]
""
"@
lsrb
+ lsr\\t%b0
lsr\\t%b0
lsr%0
#")