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SH: use register names instead of numbers


This patch replaces all references to literal register numbers in the
SH-specific configuration files with far more readable macros.  In the
case of the md file, a sed script is created out of #defines in the
new sh-md.h, and this script is used to edit sh.md.

I haven't completed testing of this patch, but I'm getting a lot of
failures with -O3 -fPIC that I believe not to have been introduced by
this patch.  Many mova insns are being modified so as to set other
registers, and then the insn becomes unrecognizable because mova can
only set r0.  I'll investigate.

Anyway, assuming the problem is not introduced by this patch (which
I'm going to verify before installing it), ok to install?

Index: ChangeLog
from  Alexandre Oliva  <aoliva@redhat.com>

	* config/sh/sh.h (FIRST_GENERAL_REG, LAST_GENERAL_REG): New.
	(SPECIAL_REG): Renamed to SPECIAL_REGISTER_P.
	(GENERAL_REGISTER_P, GENERAL_OR_AP_REGISTER_P, FP_REGISTER_P,
	XD_REGISTER_P): New.  Use them all over.
	Moved most register-number #defines...
	* config/sh/sh-md.h: ... here.  New file.
	* config/sh/sh.c: Always use macros to refer to register numbers.
	* config/sh/sh.md: Likewise.
	* config/sh/t-sh (md_file, md-sed, md): New rules to
	preprocess sh.md with a sed-script derived from sh-md.h
	(clean, sh-clean): Remove the new generated files.
	* configure.in (tm_file) [sh-*]: Add sh/sh-md.h.
	* configure: Rebuilt.

Index: gcc/configure.in
===================================================================
RCS file: /cvs/gcc/egcs/gcc/configure.in,v
retrieving revision 1.452
diff -u -p -r1.452 configure.in
--- gcc/configure.in 2000/11/15 04:40:30 1.452
+++ gcc/configure.in 2000/11/16 09:05:40
@@ -3420,21 +3420,21 @@ changequote([,])dnl
 		;;
 	sh-*-elf*)
 		tmake_file="sh/t-sh sh/t-elf"
-		tm_file="sh/sh.h sh/elf.h"
+		tm_file="sh/sh-md.h sh/sh.h sh/elf.h"
 		float_format=sh
 		;;
 	sh-*-rtemself*)
 		tmake_file="sh/t-sh sh/t-elf t-rtems"
-		tm_file="sh/sh.h sh/elf.h sh/rtemself.h"
+		tm_file="sh/sh-md.h sh/sh.h sh/elf.h sh/rtemself.h"
 		float_format=sh
 		;;
 	sh-*-rtems*)
 		tmake_file="sh/t-sh t-rtems"
-		tm_file="sh/sh.h sh/rtems.h"
+		tm_file="sh/sh-md.h sh/sh.h sh/rtems.h"
 		float_format=sh
 		;;
 	sh-*-linux*)
-		tm_file="sh/sh.h sh/elf.h sh/linux.h"
+		tm_file="sh/sh-md.h sh/sh.h sh/elf.h sh/linux.h"
 		tmake_file="sh/t-sh sh/t-elf sh/t-linux"
 		xmake_file=x-linux
 		gas=yes gnu_ld=yes
@@ -3444,6 +3444,7 @@ changequote([,])dnl
 		float_format=sh
 		;;
 	sh-*-*)
+		tm_file="sh/sh-md.h sh/sh.h"
 		float_format=sh
 		;;
 	sparc-tti-*)
Index: gcc/config/sh/sh-md.h
===================================================================
RCS file: sh-md.h
diff -N sh-md.h
--- /dev/null	Tue May  5 13:32:27 1998
+++ gcc/config/sh/sh-md.h Thu Nov 16 01:05:40 2000
@@ -0,0 +1,59 @@
+/* Definitions of constants used in the machine description file.
+   Copyright (C) 2000
+   Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#ifndef GCC_SH_MD_H
+#define GCC_SH_MD_H
+
+/* All #defines in this file should define integer literals, otherwise
+   they won't be available for subsitution in the md file.  Care
+   must be taken to not add #defines that have substrings
+   referenced in the MD file.  */
+
+#define AP_REG   16
+#define PR_REG   17
+#define T_REG    18
+#define GBR_REG  19
+#define MACH_REG 20
+#define MACL_REG 21
+#define FPUL_REG 22
+#define RAP_REG  23
+
+#define FPSCR_REG 48
+
+#define PIC_REG 12
+#define FRP_REG 14
+#define SP_REG 15
+
+#define R0_REG 0
+#define R1_REG 1
+#define R2_REG 2
+#define R3_REG 3
+#define R4_REG 4
+#define R5_REG 5
+#define R6_REG 6
+
+#define DR0_REG 24
+#define DR2_REG 26
+#define DR4_REG 28
+
+#define XD0_REG 40
+
+#endif /* GCC_SH_MD_H */
Index: gcc/config/sh/sh.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.c,v
retrieving revision 1.70
diff -u -p -r1.70 sh.c
--- gcc/config/sh/sh.c 2000/11/09 07:45:15 1.70
+++ gcc/config/sh/sh.c 2000/11/16 09:05:41
@@ -302,7 +302,7 @@ print_operand (stream, x, code)
       switch (GET_CODE (x))
 	{
 	case REG:
-	  if (REGNO (x) >= FIRST_FP_REG && REGNO (x) <= LAST_FP_REG
+	  if (FP_REGISTER_P (REGNO (x))
 	      && GET_MODE_SIZE (GET_MODE (x)) > 4)
 	    fprintf ((stream), "d%s", reg_names[REGNO (x)]+1);
 	  else
@@ -598,7 +598,7 @@ from_compare (operands, code)
     }
   else
     insn = gen_rtx_SET (VOIDmode,
-			gen_rtx_REG (SImode, 18),
+			gen_rtx_REG (SImode, T_REG),
 			gen_rtx (code, SImode, sh_compare_op0,
 				 sh_compare_op1));
   if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
@@ -1596,7 +1596,7 @@ gen_shl_and (dest, left_rtx, mask_rtx, s
                                     (match_operand:SI 2 "const_int_operand" "n")
                          (match_operand:SI 3 "const_int_operand" "n")
                          (const_int 0)))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
   return 0 for simple left / right shift combination.
   return 1 for left shift / 8 bit sign extend / left shift.
@@ -2080,8 +2080,7 @@ broken_move (insn)
 		   know the current setting of fpscr, so disable fldi.  */
 		&& (! TARGET_SH4 || TARGET_FMOVD)
 		&& GET_CODE (SET_DEST (pat)) == REG
-		&& REGNO (SET_DEST (pat)) >= FIRST_FP_REG
-		&& REGNO (SET_DEST (pat)) <= LAST_FP_REG)
+		&& FP_REGISTER_P (REGNO (SET_DEST (pat))))
 	  && (GET_CODE (SET_SRC (pat)) != CONST_INT
 	      || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
 	return 1;
@@ -2206,8 +2205,8 @@ find_barrier (num_mova, mova, from)
 	  /* See the code in machine_dependent_reorg, which has a similar if
 	     statement that generates new mova insn in many cases.  */
 	  if (GET_CODE (dst) == REG
-	      && ((REGNO (dst) >= FIRST_FP_REG
-		   && REGNO (dst) <= LAST_XD_REG)
+	      && (FP_REGISTER_P (REGNO (dst))
+		  || XD_REGISTER_P (REGNO (dst))
 		  || REGNO (dst) == FPUL_REG))
 	    inc += 2;
 	}
@@ -3232,8 +3231,8 @@ machine_dependent_reorg (first)
 		    }
 
 		  if (GET_CODE (dst) == REG
-		      && ((REGNO (dst) >= FIRST_FP_REG
-			   && REGNO (dst) <= LAST_XD_REG)
+		      && (FP_REGISTER_P (REGNO (dst))
+			  || XD_REGISTER_P (REGNO (dst))
 			  || REGNO (dst) == FPUL_REG))
 		    {
 		      /* This must be an insn that clobbers r0.  */
@@ -3743,13 +3742,13 @@ push (rn)
   if (rn == FPUL_REG)
     x = gen_push_fpul ();
   else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
-	   && rn >= FIRST_FP_REG && rn <= LAST_XD_REG)
+	   && (FP_REGISTER_P (rn) || XD_REGISTER_P (rn)))
     {
-      if ((rn - FIRST_FP_REG) & 1 && rn <= LAST_FP_REG)
+      if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
 	return;
       x = gen_push_4 (gen_rtx_REG (DFmode, rn));
     }
-  else if (TARGET_SH3E && rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
+  else if (TARGET_SH3E && FP_REGISTER_P (rn))
     x = gen_push_e (gen_rtx_REG (SFmode, rn));
   else
     x = gen_push (gen_rtx_REG (SImode, rn));
@@ -3770,13 +3769,13 @@ pop (rn)
   if (rn == FPUL_REG)
     x = gen_pop_fpul ();
   else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
-	   && rn >= FIRST_FP_REG && rn <= LAST_XD_REG)
+	   && (FP_REGISTER_P (rn) || XD_REGISTER_P (rn)))
     {
-      if ((rn - FIRST_FP_REG) & 1 && rn <= LAST_FP_REG)
+      if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
 	return;
       x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
     }
-  else if (TARGET_SH3E && rn >= FIRST_FP_REG && rn <= LAST_FP_REG)
+  else if (TARGET_SH3E && FP_REGISTER_P (rn))
     x = gen_pop_e (gen_rtx_REG (SFmode, rn));
   else
     x = gen_pop (gen_rtx_REG (SImode, rn));
@@ -3863,9 +3862,10 @@ calc_live_regs (count_ptr, live_regs_mas
 	  else
 	    live_regs_mask |= 1 << reg;
 	  count++;
-	  if (TARGET_SH4 && TARGET_FMOVD && reg >= FIRST_FP_REG)
+	  if (TARGET_SH4 && TARGET_FMOVD
+	      && (FP_REGISTER_P (reg) || XD_REGISTER_P (reg)))
 	    {
-	      if (reg <= LAST_FP_REG)
+	      if (FP_REGISTER_P (reg))
 		{
 		  if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
 		    {
@@ -3876,12 +3876,14 @@ calc_live_regs (count_ptr, live_regs_mas
 		      count++;
 		    }
 		}
-	      else if (reg <= LAST_XD_REG)
+	      else if (XD_REGISTER_P (reg))
 		{
 		  /* Must switch to double mode to access these registers.  */
 		  target_flags &= ~FPU_SINGLE_BIT;
 		  count++;
 		}
+	      else
+		abort ();
 	    }
 	}
     }
@@ -4701,7 +4703,7 @@ fp_arith_reg_operand (op, mode)
 	return 1;
 
       return (regno >= FIRST_PSEUDO_REGISTER
-	      || (regno >= FIRST_FP_REG && regno <= LAST_FP_REG));
+	      || FP_REGISTER_P (regno));
     }
   return 0;
 }
@@ -5000,7 +5002,7 @@ get_fpscr_rtx ()
 
   if (! fpscr_rtx)
     {
-      fpscr_rtx = gen_rtx (REG, PSImode, 48);
+      fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
       REG_USERVAR_P (fpscr_rtx) = 1;
       ggc_add_rtx_root (&fpscr_rtx, 1);
       mark_user_reg (fpscr_rtx);
Index: gcc/config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.h,v
retrieving revision 1.82
diff -u -p -r1.82 sh.h
--- gcc/config/sh/sh.h 2000/11/11 05:54:02 1.82
+++ gcc/config/sh/sh.h 2000/11/16 09:05:42
@@ -432,21 +432,31 @@ do {									\
    All registers that the compiler knows about must be given numbers,
    even those that are not normally considered general registers.  */
 
-#define AP_REG   16
-#define PR_REG   17
-#define T_REG    18
-#define GBR_REG  19
-#define MACH_REG 20
-#define MACL_REG 21
-#define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
-#define FPUL_REG 22
-#define RAP_REG 23
-#define FIRST_FP_REG 24
-#define LAST_FP_REG 39
-#define FIRST_XD_REG 40
-#define LAST_XD_REG 47
-#define FPSCR_REG 48
+/* There are many other relevant definitions in sh-md.h  */
 
+#define FIRST_GENERAL_REG R0_REG
+#define LAST_GENERAL_REG FIRST_GENERAL_REG + 15
+#define FIRST_FP_REG DR0_REG
+#define LAST_FP_REG  FIRST_FP_REG + 15
+#define FIRST_XD_REG XD0_REG
+#define LAST_XD_REG  FIRST_XD_REG + 7
+
+#define GENERAL_REGISTER_P(REGNO) \
+  ((REGNO) >= FIRST_GENERAL_REG && (REGNO) <= LAST_GENERAL_REG)
+
+#define GENERAL_OR_AP_REGISTER_P(REGNO) \
+  (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
+
+#define FP_REGISTER_P(REGNO) \
+  ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
+
+#define XD_REGISTER_P(REGNO) \
+  ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
+
+#define SPECIAL_REGISTER_P(REGNO) \
+  ((REGNO) == GBR_REG || (REGNO) == T_REG \
+   || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
+
 #define FIRST_PSEUDO_REGISTER 49
 
 /* 1 for registers that have pervasive standard uses
@@ -502,7 +512,7 @@ do {									\
    On the SH all but the XD regs are UNITS_PER_WORD bits wide.  */
 
 #define HARD_REGNO_NREGS(REGNO, MODE) \
-   ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \
+   (XD_REGISTER_P (REGNO) \
     ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
     : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
 
@@ -519,16 +529,16 @@ do {									\
    and a secondary reload to reload from / to general regs; that
    seems to be a loosing proposition.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE)		\
-  (SPECIAL_REG (REGNO) ? (MODE) == SImode	\
+  (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
    : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode	\
-   : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG && (MODE) == SFmode \
+   : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
    ? 1 \
-   : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG \
+   : FP_REGISTER_P (REGNO) \
    ? ((MODE) == SFmode \
       || (TARGET_SH3E && (MODE) == SCmode) \
       || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \
 	  && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
-   : (REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \
+   : XD_REGISTER_P (REGNO) \
    ? (MODE) == DFmode \
    : (REGNO) == PR_REG ? 0			\
    : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
@@ -554,18 +564,18 @@ do {									\
 /* #define PC_REGNUM		15*/
 
 /* Register to use for pushing function arguments.  */
-#define STACK_POINTER_REGNUM	15
+#define STACK_POINTER_REGNUM	SP_REG
 
 /* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM	14
+#define FRAME_POINTER_REGNUM	FRP_REG
 
 /* Fake register that holds the address on the stack of the
    current function's return address.  */
-#define RETURN_ADDRESS_POINTER_REGNUM 23
+#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
 
 /* Register to hold the addressing base for position independent
    code access to data items.  */
-#define PIC_OFFSET_TABLE_REGNUM	12
+#define PIC_OFFSET_TABLE_REGNUM	PIC_REG
 
 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
 
@@ -817,10 +827,10 @@ extern enum reg_class reg_class_from_let
 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
   ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS			\
 	|| (CLASS) == DF_REGS)						\
-      && (GET_CODE (X) == REG && REGNO (X) <= AP_REG))			\
+      && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X))))	\
      || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS)		\
 	 && GET_CODE (X) == REG						\
-	 && REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG))	\
+	 && FP_REGISTER_P (REGNO (X))))					\
     && MODE == SFmode)							\
    ? FPUL_REGS								\
    : ((CLASS) == FPUL_REGS						\
@@ -831,7 +841,7 @@ extern enum reg_class reg_class_from_let
 		  || system_reg_operand (X, VOIDmode)))))		\
    ? GENERAL_REGS							\
    : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS)			\
-      && GET_CODE (X) == REG && REGNO (X) > 15				\
+      && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X))	\
       && (CLASS) != REGNO_REG_CLASS (REGNO (X)))			\
    ? GENERAL_REGS : NO_REGS)
 
@@ -886,8 +896,8 @@ extern enum reg_class reg_class_from_let
    ? 8 \
    : 4)
 
-#define FIRST_PARM_REG 4
-#define FIRST_RET_REG  0
+#define FIRST_PARM_REG (FIRST_GENERAL_REG + 4)
+#define FIRST_RET_REG  FIRST_GENERAL_REG
 
 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
 #define FIRST_FP_RET_REG FIRST_FP_REG
@@ -1267,9 +1277,10 @@ extern int current_function_anonymous_ar
    has been allocated, which happens in local-alloc.c.  */
 
 #define REGNO_OK_FOR_BASE_P(REGNO) \
-  ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
+  (GENERAL_OR_AP_REGISTER_P (REGNO) \
+   || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
 #define REGNO_OK_FOR_INDEX_P(REGNO) \
-  ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
+  ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
 
 /* Maximum number of registers that can appear in a valid memory
    address.  */
@@ -1299,17 +1310,17 @@ extern int current_function_anonymous_ar
 /* Nonzero if X is a hard reg that can be used as a base reg
    or if it is a pseudo reg.  */
 #define REG_OK_FOR_BASE_P(X) \
-  (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+  (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
 
 /* Nonzero if X is a hard reg that can be used as an index
    or if it is a pseudo reg.  */
 #define REG_OK_FOR_INDEX_P(X) \
-  (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+  (REGNO (X) == R0_REG || REGNO (X) >= FIRST_PSEUDO_REGISTER)
 
 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
    or if X is a pseudo reg.  */
 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
-  ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+  ((REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
 
 #else
 
Index: gcc/config/sh/sh.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/sh.md,v
retrieving revision 1.55
diff -u -p -r1.55 sh.md
--- gcc/config/sh/sh.md 2000/11/10 16:01:27 1.55
+++ gcc/config/sh/sh.md 2000/11/16 09:05:42
@@ -68,6 +68,9 @@
 ;; Attributes
 ;; -------------------------------------------------------------------------
 
+;; This file is preprocessed, having all #defines in sh-md.h replaced
+;; with the corresponding constants.  See t-sh for the rules to do it.
+
 ;; Target CPU.
 
 (define_attr "cpu"
@@ -536,7 +539,7 @@
 ;; -------------------------------------------------------------------------
 
 (define_insn ""
-  [(set (reg:SI 18)
+  [(set (reg:SI T_REG)
 	(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
 		       (match_operand:SI 1 "arith_operand" "L,r"))
 	       (const_int 0)))]
@@ -550,8 +553,9 @@
 ;; register for pseudo/imm compares.
 
 (define_insn "cmpeqsi_t"
-  [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
-			   (match_operand:SI 1 "arith_operand" "N,rI,r")))]
+  [(set (reg:SI T_REG)
+	(eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
+	       (match_operand:SI 1 "arith_operand" "N,rI,r")))]
   ""
   "@
 	tst	%0,%0
@@ -559,16 +563,18 @@
 	cmp/eq	%1,%0")
 
 (define_insn "cmpgtsi_t"
-  [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
-			   (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
+  [(set (reg:SI T_REG)
+	(gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
+	       (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
   ""
   "@
 	cmp/gt	%1,%0
 	cmp/pl	%0")
 
 (define_insn "cmpgesi_t"
-  [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
-			   (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
+  [(set (reg:SI T_REG)
+	(ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
+	       (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
   ""
   "@
 	cmp/ge	%1,%0
@@ -579,14 +585,16 @@
 ;; -------------------------------------------------------------------------
 
 (define_insn "cmpgeusi_t"
-  [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
-			    (match_operand:SI 1 "arith_reg_operand" "r")))]
+  [(set (reg:SI T_REG)
+	(geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
+		(match_operand:SI 1 "arith_reg_operand" "r")))]
   ""
   "cmp/hs	%1,%0")
 
 (define_insn "cmpgtusi_t"
-  [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
-			    (match_operand:SI 1 "arith_reg_operand" "r")))]
+  [(set (reg:SI T_REG)
+	(gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
+		(match_operand:SI 1 "arith_reg_operand" "r")))]
   ""
   "cmp/hi	%1,%0")
 
@@ -594,8 +602,9 @@
 ;; we generate the branch.
 
 (define_expand "cmpsi"
-  [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "")
-			     (match_operand:SI 1 "arith_operand" "")))]
+  [(set (reg:SI T_REG)
+	(compare (match_operand:SI 0 "arith_operand" "")
+		 (match_operand:SI 1 "arith_operand" "")))]
   ""
   "
 {
@@ -613,7 +622,7 @@
 ;; the sh.md size increase necessary to do that.
 
 (define_insn ""
-  [(set (reg:SI 18)
+  [(set (reg:SI T_REG)
 	(eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
 		       (match_operand:DI 1 "arith_operand" "r"))
 	       (const_int 0)))]
@@ -624,8 +633,9 @@
    (set_attr "type" "arith3b")])
 
 (define_insn "cmpeqdi_t"
-  [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
-			   (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
+  [(set (reg:SI T_REG)
+	(eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
+	       (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
   ""
   "@
 	tst	%S0,%S0\;bf	%,Ldi%=\;tst	%R0,%R0\\n%,Ldi%=:
@@ -634,17 +644,18 @@
    (set_attr "type" "arith3b")])
 
 (define_split
-  [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
-			   (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
+  [(set (reg:SI T_REG)
+	(eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
+	       (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
 ;; If we applied this split when not optimizing, it would only be
 ;; applied during the machine-dependent reorg, when no new basic blocks
 ;; may be created.
   "reload_completed && optimize"
-  [(set (reg:SI 18) (eq:SI (match_dup 2) (match_dup 3)))
-   (set (pc) (if_then_else (eq (reg:SI 18) (const_int 0))
+  [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
+   (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
 			   (label_ref (match_dup 6))
 			   (pc)))
-   (set (reg:SI 18) (eq:SI (match_dup 4) (match_dup 5)))
+   (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
    (match_dup 6)]
   "
 {
@@ -663,8 +674,9 @@
 }")
 
 (define_insn "cmpgtdi_t"
-  [(set (reg:SI 18) (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
-			   (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
+  [(set (reg:SI T_REG)
+	(gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
+	       (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
   "TARGET_SH2"
   "@
 	cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
@@ -673,8 +685,9 @@
    (set_attr "type" "arith3")])
 
 (define_insn "cmpgedi_t"
-  [(set (reg:SI 18) (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
-			   (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
+  [(set (reg:SI T_REG)
+	(ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
+	       (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
   "TARGET_SH2"
   "@
 	cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
@@ -687,16 +700,18 @@
 ;; -------------------------------------------------------------------------
 
 (define_insn "cmpgeudi_t"
-  [(set (reg:SI 18) (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
-			    (match_operand:DI 1 "arith_reg_operand" "r")))]
+  [(set (reg:SI T_REG)
+	(geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
+		(match_operand:DI 1 "arith_reg_operand" "r")))]
   "TARGET_SH2"
   "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
   [(set_attr "length" "8")
    (set_attr "type" "arith3")])
 
 (define_insn "cmpgtudi_t"
-  [(set (reg:SI 18) (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
-			    (match_operand:DI 1 "arith_reg_operand" "r")))]
+  [(set (reg:SI T_REG)
+	(gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
+		(match_operand:DI 1 "arith_reg_operand" "r")))]
   "TARGET_SH2"
   "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
   [(set_attr "length" "8")
@@ -706,8 +721,9 @@
 ;; we generate the branch.
 
 (define_expand "cmpdi"
-  [(set (reg:SI 18) (compare (match_operand:DI 0 "arith_operand" "")
-			     (match_operand:DI 1 "arith_operand" "")))]
+  [(set (reg:SI T_REG)
+	(compare (match_operand:DI 0 "arith_operand" "")
+		 (match_operand:DI 1 "arith_operand" "")))]
   "TARGET_SH2"
   "
 {
@@ -726,7 +742,7 @@
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
 	(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
 		 (match_operand:DI 2 "arith_reg_operand" "r")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "#"
   [(set_attr "length" "6")])
@@ -735,7 +751,7 @@
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
 	(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
 		 (match_operand:DI 2 "arith_reg_operand" "r")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "reload_completed"
   [(const_int 0)]
   "
@@ -757,8 +773,8 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
 			  (match_operand:SI 2 "arith_reg_operand" "r"))
-		 (reg:SI 18)))
-   (set (reg:SI 18)
+		 (reg:SI T_REG)))
+   (set (reg:SI T_REG)
 	(ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
   ""
   "addc	%2,%0"
@@ -768,8 +784,8 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
 			  (match_operand:SI 2 "arith_reg_operand" "r"))
-		 (reg:SI 18)))
-   (clobber (reg:SI 18))]
+		 (reg:SI T_REG)))
+   (clobber (reg:SI T_REG))]
   ""
   "addc	%2,%0"
   [(set_attr "type" "arith")])
@@ -792,7 +808,7 @@
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
 	(minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
 		 (match_operand:DI 2 "arith_reg_operand" "r")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "#"
   [(set_attr "length" "6")])
@@ -801,7 +817,7 @@
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
 	(minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
 		  (match_operand:DI 2 "arith_reg_operand" "r")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "reload_completed"
   [(const_int 0)]
   "
@@ -823,8 +839,8 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
 			    (match_operand:SI 2 "arith_reg_operand" "r"))
-		  (reg:SI 18)))
-   (set (reg:SI 18)
+		  (reg:SI T_REG)))
+   (set (reg:SI T_REG)
 	(gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
   ""
   "subc	%2,%0"
@@ -834,8 +850,8 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
 			    (match_operand:SI 2 "arith_reg_operand" "r"))
-		  (reg:SI 18)))
-   (clobber (reg:SI 18))]
+		  (reg:SI T_REG)))
+   (clobber (reg:SI T_REG))]
   ""
   "subc	%2,%0"
   [(set_attr "type" "arith")])
@@ -881,7 +897,8 @@
 ;; of this register for reorg.
 
 (define_insn "use_sfunc_addr"
-  [(set (reg:SI 17) (unspec [(match_operand:SI 0 "register_operand" "r")] 5))]
+  [(set (reg:SI PR_REG)
+	(unspec [(match_operand:SI 0 "register_operand" "r")] 5))]
   ""
   ""
   [(set_attr "length" "0")])
@@ -896,10 +913,10 @@
 
 (define_insn "udivsi3_i1"
   [(set (match_operand:SI 0 "register_operand" "=z")
-	(udiv:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 18))
-   (clobber (reg:SI 17))
-   (clobber (reg:SI 4))
+	(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+   (clobber (reg:SI T_REG))
+   (clobber (reg:SI PR_REG))
+   (clobber (reg:SI R4_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r"))]
   "! TARGET_SH4"
   "jsr	@%1%#"
@@ -908,16 +925,16 @@
 
 (define_insn "udivsi3_i4"
   [(set (match_operand:SI 0 "register_operand" "=y")
-	(udiv:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 17))
-   (clobber (reg:DF 24))
-   (clobber (reg:DF 26))
-   (clobber (reg:DF 28))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 4))
-   (clobber (reg:SI 5))
-   (use (reg:PSI 48))
+	(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+   (clobber (reg:SI PR_REG))
+   (clobber (reg:DF DR0_REG))
+   (clobber (reg:DF DR2_REG))
+   (clobber (reg:DF DR4_REG))
+   (clobber (reg:SI R0_REG))
+   (clobber (reg:SI R1_REG))
+   (clobber (reg:SI R4_REG))
+   (clobber (reg:SI R5_REG))
+   (use (reg:PSI FPSCR_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r"))]
   "TARGET_SH4 && ! TARGET_FPU_SINGLE"
   "jsr	@%1%#"
@@ -927,15 +944,15 @@
 
 (define_insn "udivsi3_i4_single"
   [(set (match_operand:SI 0 "register_operand" "=y")
-	(udiv:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 17))
-   (clobber (reg:DF 24))
-   (clobber (reg:DF 26))
-   (clobber (reg:DF 28))
-   (clobber (reg:SI 0))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 4))
-   (clobber (reg:SI 5))
+	(udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+   (clobber (reg:SI PR_REG))
+   (clobber (reg:DF DR0_REG))
+   (clobber (reg:DF DR2_REG))
+   (clobber (reg:DF DR4_REG))
+   (clobber (reg:SI R0_REG))
+   (clobber (reg:SI R1_REG))
+   (clobber (reg:SI R4_REG))
+   (clobber (reg:SI R5_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r"))]
   "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
   "jsr	@%1%#"
@@ -944,14 +961,14 @@
 
 (define_expand "udivsi3"
   [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
-   (set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
-   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
+   (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
+   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
    (parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (udiv:SI (reg:SI 4)
-			    (reg:SI 5)))
-	      (clobber (reg:SI 18))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 4))
+		   (udiv:SI (reg:SI R4_REG)
+			    (reg:SI R5_REG)))
+	      (clobber (reg:SI T_REG))
+	      (clobber (reg:SI PR_REG))
+	      (clobber (reg:SI R4_REG))
 	      (use (match_dup 3))])]
   ""
   "
@@ -987,12 +1004,12 @@
 
 (define_insn "divsi3_i1"
   [(set (match_operand:SI 0 "register_operand" "=z")
-	(div:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 18))
-   (clobber (reg:SI 17))
-   (clobber (reg:SI 1))
-   (clobber (reg:SI 2))
-   (clobber (reg:SI 3))
+	(div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+   (clobber (reg:SI T_REG))
+   (clobber (reg:SI PR_REG))
+   (clobber (reg:SI R1_REG))
+   (clobber (reg:SI R2_REG))
+   (clobber (reg:SI R3_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r"))]
   "! TARGET_SH4"
   "jsr	@%1%#"
@@ -1001,11 +1018,11 @@
 
 (define_insn "divsi3_i4"
   [(set (match_operand:SI 0 "register_operand" "=y")
-	(div:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 17))
-   (clobber (reg:DF 24))
-   (clobber (reg:DF 26))
-   (use (reg:PSI 48))
+	(div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+   (clobber (reg:SI PR_REG))
+   (clobber (reg:DF DR0_REG))
+   (clobber (reg:DF DR2_REG))
+   (use (reg:PSI FPSCR_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r"))]
   "TARGET_SH4 && ! TARGET_FPU_SINGLE"
   "jsr	@%1%#"
@@ -1015,11 +1032,11 @@
 
 (define_insn "divsi3_i4_single"
   [(set (match_operand:SI 0 "register_operand" "=y")
-	(div:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 17))
-   (clobber (reg:DF 24))
-   (clobber (reg:DF 26))
-   (clobber (reg:SI 2))
+	(div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+   (clobber (reg:SI PR_REG))
+   (clobber (reg:DF DR0_REG))
+   (clobber (reg:DF DR2_REG))
+   (clobber (reg:SI R2_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r"))]
   "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
   "jsr	@%1%#"
@@ -1028,16 +1045,16 @@
 
 (define_expand "divsi3"
   [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
-   (set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
-   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
+   (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
+   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
    (parallel [(set (match_operand:SI 0 "register_operand" "")
-		   (div:SI (reg:SI 4)
-			   (reg:SI 5)))
-	      (clobber (reg:SI 18))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 1))
-	      (clobber (reg:SI 2))
-	      (clobber (reg:SI 3))
+		   (div:SI (reg:SI R4_REG)
+			   (reg:SI R5_REG)))
+	      (clobber (reg:SI T_REG))
+	      (clobber (reg:SI PR_REG))
+	      (clobber (reg:SI R1_REG))
+	      (clobber (reg:SI R2_REG))
+	      (clobber (reg:SI R3_REG))
 	      (use (match_dup 3))])]
   ""
   "
@@ -1075,7 +1092,7 @@
 ;; -------------------------------------------------------------------------
 
 (define_insn "umulhisi3_i"
-  [(set (reg:SI 21)
+  [(set (reg:SI MACL_REG)
 	(mult:SI (zero_extend:SI (match_operand:HI 0 "arith_reg_operand" "r"))
 		 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))))]
   ""
@@ -1083,7 +1100,7 @@
   [(set_attr "type" "smpy")])
 
 (define_insn "mulhisi3_i"
-  [(set (reg:SI 21)
+  [(set (reg:SI MACL_REG)
 	(mult:SI (sign_extend:SI
 		  (match_operand:HI 0 "arith_reg_operand" "r"))
 		 (sign_extend:SI
@@ -1093,20 +1110,20 @@
   [(set_attr "type" "smpy")])
 
 (define_expand "mulhisi3"
-  [(set (reg:SI 21)
+  [(set (reg:SI MACL_REG)
 	(mult:SI (sign_extend:SI
 		  (match_operand:HI 1 "arith_reg_operand" ""))
 		 (sign_extend:SI
 		  (match_operand:HI 2 "arith_reg_operand" ""))))
    (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 21))]
+	(reg:SI MACL_REG))]
   ""
   "
 {
   rtx first, last;
 
   first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
-  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
+  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
   /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
      invariant code motion can move it.  */
   REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
@@ -1115,20 +1132,20 @@
 }")
 
 (define_expand "umulhisi3"
-  [(set (reg:SI 21)
+  [(set (reg:SI MACL_REG)
 	(mult:SI (zero_extend:SI
 		  (match_operand:HI 1 "arith_reg_operand" ""))
 		 (zero_extend:SI
 		  (match_operand:HI 2 "arith_reg_operand" ""))))
    (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 21))]
+	(reg:SI MACL_REG))]
   ""
   "
 {
   rtx first, last;
 
   first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
-  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
+  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
   /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
      invariant code motion can move it.  */
   REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
@@ -1141,13 +1158,13 @@
 
 (define_insn ""
   [(set (match_operand:SI 1 "register_operand" "=z")
-	(mult:SI (reg:SI 4) (reg:SI 5)))
-   (clobber (reg:SI 21))
-   (clobber (reg:SI 18))
-   (clobber (reg:SI 17))
-   (clobber (reg:SI 3))
-   (clobber (reg:SI 2))
-   (clobber (reg:SI 1))
+	(mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+   (clobber (reg:SI MACL_REG))
+   (clobber (reg:SI T_REG))
+   (clobber (reg:SI PR_REG))
+   (clobber (reg:SI R3_REG))
+   (clobber (reg:SI R2_REG))
+   (clobber (reg:SI R1_REG))
    (use (match_operand:SI 0 "arith_reg_operand" "r"))]
   ""
   "jsr	@%0%#"
@@ -1155,23 +1172,23 @@
    (set_attr "needs_delay_slot" "yes")])
 
 (define_expand "mulsi3_call"
-  [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
-   (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
+  [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
+   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
    (parallel[(set (match_operand:SI 0 "register_operand" "")
-		  (mult:SI (reg:SI 4)
-			   (reg:SI 5)))
-	     (clobber (reg:SI 21))
-	     (clobber (reg:SI 18))
-	     (clobber (reg:SI 17))
-	     (clobber (reg:SI 3))
-	     (clobber (reg:SI 2))
-	     (clobber (reg:SI 1))
+		  (mult:SI (reg:SI R4_REG)
+			   (reg:SI R5_REG)))
+	     (clobber (reg:SI MACL_REG))
+	     (clobber (reg:SI T_REG))
+	     (clobber (reg:SI PR_REG))
+	     (clobber (reg:SI R3_REG))
+	     (clobber (reg:SI R2_REG))
+	     (clobber (reg:SI R1_REG))
 	     (use (match_operand:SI 3 "register_operand" ""))])]
   ""
   "")
 
 (define_insn "mul_l"
-  [(set (reg:SI 21)
+  [(set (reg:SI MACL_REG)
 	(mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
 		 (match_operand:SI 1 "arith_reg_operand" "r")))]
   "TARGET_SH2"
@@ -1179,11 +1196,11 @@
   [(set_attr "type" "dmpy")])
 
 (define_expand "mulsi3"
-  [(set (reg:SI 21)
+  [(set (reg:SI MACL_REG)
 	(mult:SI  (match_operand:SI 1 "arith_reg_operand" "")
 		  (match_operand:SI 2 "arith_reg_operand" "")))
    (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 21))]
+	(reg:SI MACL_REG))]
   ""
   "
 {
@@ -1219,12 +1236,14 @@
 }")
 
 (define_insn "mulsidi3_i"
-  [(set (reg:SI 20)
+  [(set (reg:SI MACH_REG)
 	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
-			       (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
-		      (const_int 32))))
-   (set (reg:SI 21)
+	 (lshiftrt:DI
+	  (mult:DI
+	   (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
+	   (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
+	  (const_int 32))))
+   (set (reg:SI MACL_REG)
 	(mult:SI (match_dup 0)
 		 (match_dup 1)))]
   "TARGET_SH2"
@@ -1233,17 +1252,21 @@
 
 (define_insn "mulsidi3"
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
-		 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
-   (clobber (reg:DI 20))]
+	(mult:DI
+	 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
+	 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
+   (clobber (reg:SI MACH_REG))
+   (clobber (reg:SI MACL_REG))]
   "TARGET_SH2"
   "#")
 
 (define_split
   [(set (match_operand:DI 0 "arith_reg_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
-		 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
-   (clobber (reg:DI 20))]
+	(mult:DI
+	 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
+	 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
+   (clobber (reg:SI MACH_REG))
+   (clobber (reg:SI MACL_REG))]
   "TARGET_SH2"
   [(const_int 0)]
   "
@@ -1253,20 +1276,22 @@
 
   emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
 
-  emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
-  emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
+  emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
+  emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
   /* We need something to tag the possible REG_EQUAL notes on to.  */
   emit_move_insn (operands[0], operands[0]);
   DONE;
 }")
 
 (define_insn "umulsidi3_i"
-  [(set (reg:SI 20)
+  [(set (reg:SI MACH_REG)
 	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
-			       (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
-		      (const_int 32))))
-   (set (reg:SI 21)
+	 (lshiftrt:DI
+	  (mult:DI
+	   (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
+	   (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
+	  (const_int 32))))
+   (set (reg:SI MACL_REG)
 	(mult:SI (match_dup 0)
 		 (match_dup 1)))]
   "TARGET_SH2"
@@ -1275,9 +1300,11 @@
 
 (define_insn "umulsidi3"
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
-		 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
-   (clobber (reg:DI 20))]
+	(mult:DI
+	 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
+	 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
+   (clobber (reg:SI MACH_REG))
+   (clobber (reg:SI MACL_REG))]
   "TARGET_SH2"
   "#")
 
@@ -1285,7 +1312,8 @@
   [(set (match_operand:DI 0 "arith_reg_operand" "")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
 		 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
-   (clobber (reg:DI 20))]
+   (clobber (reg:SI MACH_REG))
+   (clobber (reg:SI MACL_REG))]
   "TARGET_SH2"
   [(const_int 0)]
   "
@@ -1295,40 +1323,45 @@
 
   emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
 
-  emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
-  emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
+  emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
+  emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
   /* We need something to tag the possible REG_EQUAL notes on to.  */
   emit_move_insn (operands[0], operands[0]);
   DONE;
 }")
 
 (define_insn "smulsi3_highpart_i"
-  [(set (reg:SI 20)
+  [(set (reg:SI MACH_REG)
 	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
-			       (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
-		      (const_int 32))))
-   (clobber (reg:SI 21))]
+	 (lshiftrt:DI
+	  (mult:DI
+	   (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
+	   (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
+	  (const_int 32))))
+   (clobber (reg:SI MACL_REG))]
   "TARGET_SH2"
   "dmuls.l	%1,%0"
   [(set_attr "type" "dmpy")])
 
 (define_expand "smulsi3_highpart"
-  [(parallel [(set (reg:SI 20)
-		   (truncate:SI
-		    (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
-					  (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
-				 (const_int 32))))
-	      (clobber (reg:SI 21))])
+  [(parallel
+    [(set (reg:SI MACH_REG)
+	  (truncate:SI
+	   (lshiftrt:DI
+	    (mult:DI
+	     (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
+	     (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
+	    (const_int 32))))
+    (clobber (reg:SI MACL_REG))])
    (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 20))]
+	(reg:SI MACH_REG))]
   "TARGET_SH2"
   "
 {
   rtx first, last;
 
   first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
-  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
+  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
   /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
      invariant code motion can move it.  */
   REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
@@ -1344,32 +1377,37 @@
 }")
 
 (define_insn "umulsi3_highpart_i"
-  [(set (reg:SI 20)
+  [(set (reg:SI MACH_REG)
 	(truncate:SI
-	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
-			       (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
-		      (const_int 32))))
-   (clobber (reg:SI 21))]
+	 (lshiftrt:DI
+	  (mult:DI
+	   (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
+	   (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
+	  (const_int 32))))
+   (clobber (reg:SI MACL_REG))]
   "TARGET_SH2"
   "dmulu.l	%1,%0"
   [(set_attr "type" "dmpy")])
 
 (define_expand "umulsi3_highpart"
-  [(parallel [(set (reg:SI 20)
-		   (truncate:SI
-		    (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
-					  (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
-				 (const_int 32))))
-	      (clobber (reg:SI 21))])
+  [(parallel
+    [(set (reg:SI MACH_REG)
+	  (truncate:SI
+	   (lshiftrt:DI
+	    (mult:DI
+	     (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
+	     (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
+	    (const_int 32))))
+    (clobber (reg:SI MACL_REG))])
    (set (match_operand:SI 0 "arith_reg_operand" "")
-	(reg:SI 20))]
+	(reg:SI MACH_REG))]
   "TARGET_SH2"
   "
 {
   rtx first, last;
 
   first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
-  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
+  last = emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
   /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
      invariant code motion can move it.  */
   REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
@@ -1431,7 +1469,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
 		   (const_int 1)))
-   (set (reg:SI 18)
+   (set (reg:SI T_REG)
 	(lshiftrt:SI (match_dup 1) (const_int 31)))]
   ""
   "rotl	%0"
@@ -1441,7 +1479,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
 		   (const_int 31)))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "rotr	%0"
   [(set_attr "type" "arith")])
@@ -1573,7 +1611,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
 		   (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "! sh_dynamicalize_shift_p (operands[2])"
   "#"
   [(set (attr "length")
@@ -1590,9 +1628,9 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "")
 	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
 		   (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "
 {
   gen_shifty_op (ASHIFT, operands);
@@ -1603,7 +1641,7 @@
   [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
 		   (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
 			      (match_operand:SI 2 "nonmemory_operand" "")))
-	      (clobber (reg:SI 18))])]
+	      (clobber (reg:SI T_REG))])]
   ""
   "
 {
@@ -1623,7 +1661,7 @@
   [(set (match_operand:HI 0 "arith_reg_operand" "=r")
 	(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
 		   (match_operand:HI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "#"
   [(set (attr "length")
@@ -1638,9 +1676,9 @@
   [(set (match_operand:HI 0 "arith_reg_operand" "")
 	(ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
 		   (match_operand:HI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "
 {
   gen_shifty_hi_op (ASHIFT, operands);
@@ -1655,7 +1693,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
 		     (match_operand:SI 2 "const_int_operand" "M")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "INTVAL (operands[2]) == 1"
   "shar	%0"
   [(set_attr "type" "arith")])
@@ -1691,7 +1729,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
 		     (const_int 31)))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "#"
   [(set_attr "length" "4")])
@@ -1700,7 +1738,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
 		     (const_int 31)))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   [(const_int 0)]
   "
@@ -1713,7 +1751,7 @@
 (define_insn "ashlsi_c"
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
-   (set (reg:SI 18) (lt:SI (match_dup 1)
+   (set (reg:SI T_REG) (lt:SI (match_dup 1)
 			   (const_int 0)))]
   ""
   "shll	%0"
@@ -1728,11 +1766,11 @@
   [(set_attr "type" "dyn_shift")])
 
 (define_insn "ashrsi3_n"
-  [(set (reg:SI 4)
-	(ashiftrt:SI (reg:SI 4)
+  [(set (reg:SI R4_REG)
+	(ashiftrt:SI (reg:SI R4_REG)
 		     (match_operand:SI 0 "const_int_operand" "i")))
-   (clobber (reg:SI 18))
-   (clobber (reg:SI 17))
+   (clobber (reg:SI T_REG))
+   (clobber (reg:SI PR_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r"))]
   ""
   "jsr	@%1%#"
@@ -1743,7 +1781,7 @@
   [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
 		   (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
 				(match_operand:SI 2 "nonmemory_operand" "")))
-	      (clobber (reg:SI 18))])]
+	      (clobber (reg:SI T_REG))])]
   ""
   "if (expand_ashiftrt (operands)) DONE; else FAIL;")
 
@@ -1763,7 +1801,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
 		     (match_operand:SI 2 "const_int_operand" "M")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "CONST_OK_FOR_M (INTVAL (operands[2]))"
   "shlr	%0"
   [(set_attr "type" "arith")])
@@ -1781,7 +1819,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
 		     (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "! sh_dynamicalize_shift_p (operands[2])"
   "#"
   [(set (attr "length")
@@ -1798,9 +1836,9 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "")
 	(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
 		     (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "
 {
   gen_shifty_op (LSHIFTRT, operands);
@@ -1811,7 +1849,7 @@
   [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
 		   (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
 				(match_operand:SI 2 "nonmemory_operand" "")))
-	      (clobber (reg:SI 18))])]
+	      (clobber (reg:SI T_REG))])]
   ""
   "
 {
@@ -1835,7 +1873,7 @@
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
 	(ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
 		   (const_int 1)))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "shll	%R0\;rotcl	%S0"
   [(set_attr "length" "4")
@@ -1845,7 +1883,7 @@
   [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
 		   (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
 			      (match_operand:DI 2 "immediate_operand" "")))
-	      (clobber (reg:SI 18))])]
+	      (clobber (reg:SI T_REG))])]
   ""
   "{ if (GET_CODE (operands[2]) != CONST_INT
 	 || INTVAL (operands[2]) != 1) FAIL;} ")
@@ -1856,7 +1894,7 @@
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
 		     (const_int 1)))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "shlr	%S0\;rotcr	%R0"
   [(set_attr "length" "4")
@@ -1866,7 +1904,7 @@
   [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
 		   (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
 			       (match_operand:DI 2 "immediate_operand" "")))
-	     (clobber (reg:SI 18))])]
+	     (clobber (reg:SI T_REG))])]
   ""
   "{ if (GET_CODE (operands[2]) != CONST_INT
 	 || INTVAL (operands[2]) != 1) FAIL;} ")
@@ -1877,7 +1915,7 @@
   [(set (match_operand:DI 0 "arith_reg_operand" "=r")
 	(ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
 		     (const_int 1)))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "shar	%S0\;rotcr	%R0"
   [(set_attr "length" "4")
@@ -1887,7 +1925,7 @@
   [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
 		   (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
 				(match_operand:DI 2 "immediate_operand" "")))
-	      (clobber (reg:SI 18))])]
+	      (clobber (reg:SI T_REG))])]
   ""
   "{ if (GET_CODE (operands[2]) != CONST_INT
 	 || INTVAL (operands[2]) != 1) FAIL; } ")
@@ -1900,7 +1938,7 @@
 			   (match_operand:SI 2 "const_int_operand" "n"))
 		(match_operand:SI 3 "const_int_operand" "n")))]
   "(unsigned)INTVAL (operands[2]) < 32"
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
    DONE;")
 
@@ -1909,9 +1947,9 @@
 	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
 			   (match_operand:SI 2 "const_int_operand" "n"))
 		(match_operand:SI 3 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "(unsigned)INTVAL (operands[2]) < 32"
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
    DONE;")
 
@@ -1920,7 +1958,7 @@
 	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
 			   (match_operand:SI 2 "const_int_operand" "n"))
 		(match_operand:SI 3 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "shl_and_kind (operands[2], operands[3], 0) == 1"
  "#"
   [(set (attr "length")
@@ -1946,7 +1984,7 @@
 	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
 			   (match_operand:SI 2 "const_int_operand" "n"))
 		(match_operand:SI 3 "const_int_operand" "n")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "shl_and_kind (operands[2], operands[3], 0) == 2"
  "#"
   [(set (attr "length")
@@ -1965,12 +2003,15 @@
 ;; reload.
 (define_insn "and_shl_scratch"
   [(set (match_operand:SI 0 "register_operand" "=r,&r")
-	(lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
-						     (match_operand:SI 2 "const_int_operand" "N,n"))
-					(match_operand:SI 3 "" "0,r"))
-				(match_operand:SI 4 "const_int_operand" "n,n"))
-		     (match_operand:SI 5 "const_int_operand" "n,n")))
-   (clobber (reg:SI 18))]
+	(lshiftrt:SI
+	 (ashift:SI
+	  (and:SI
+	   (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
+			(match_operand:SI 2 "const_int_operand" "N,n"))
+	   (match_operand:SI 3 "" "0,r"))
+	  (match_operand:SI 4 "const_int_operand" "n,n"))
+	 (match_operand:SI 5 "const_int_operand" "n,n")))
+   (clobber (reg:SI T_REG))]
   ""
   "#"
   [(set (attr "length")
@@ -1987,14 +2028,17 @@
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "=r,&r")
-	(lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
-						     (match_operand:SI 2 "const_int_operand" "N,n"))
-					(match_operand:SI 3 "register_operand" "0,r"))
-				(match_operand:SI 4 "const_int_operand" "n,n"))
-		     (match_operand:SI 5 "const_int_operand" "n,n")))
-   (clobber (reg:SI 18))]
+	(lshiftrt:SI
+	 (ashift:SI
+	  (and:SI
+	   (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
+			(match_operand:SI 2 "const_int_operand" "N,n"))
+	   (match_operand:SI 3 "register_operand" "0,r"))
+	  (match_operand:SI 4 "const_int_operand" "n,n"))
+	 (match_operand:SI 5 "const_int_operand" "n,n")))
+   (clobber (reg:SI T_REG))]
   ""
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "
 {
   rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
@@ -2017,23 +2061,25 @@
 ;; signed left/right shift combination.
 (define_split
   [(set (match_operand:SI 0 "register_operand" "=r")
-        (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-				    (match_operand:SI 2 "const_int_operand" "n"))
-			 (match_operand:SI 3 "const_int_operand" "n")
-			 (const_int 0)))
-   (clobber (reg:SI 18))]
+        (sign_extract:SI
+	 (ashift:SI (match_operand:SI 1 "register_operand" "r")
+		    (match_operand:SI 2 "const_int_operand" "n"))
+	 (match_operand:SI 3 "const_int_operand" "n")
+	 (const_int 0)))
+   (clobber (reg:SI T_REG))]
   ""
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
    DONE;")
 
 (define_insn "shl_sext_ext"
   [(set (match_operand:SI 0 "register_operand" "=r")
-        (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
-				    (match_operand:SI 2 "const_int_operand" "n"))
-			 (match_operand:SI 3 "const_int_operand" "n")
-			 (const_int 0)))
-   (clobber (reg:SI 18))]
+        (sign_extract:SI
+	 (ashift:SI (match_operand:SI 1 "register_operand" "0")
+		    (match_operand:SI 2 "const_int_operand" "n"))
+	 (match_operand:SI 3 "const_int_operand" "n")
+	 (const_int 0)))
+   (clobber (reg:SI T_REG))]
   "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
   "#"
   [(set (attr "length")
@@ -2062,7 +2108,7 @@
 				    (match_operand:SI 2 "const_int_operand" "n"))
 			 (match_operand:SI 3 "const_int_operand" "n")
 			 (const_int 0)))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
   "#"
   [(set (attr "length")
@@ -2106,10 +2152,10 @@
 
 (define_insn "negc"
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(neg:SI (plus:SI (reg:SI 18)
+	(neg:SI (plus:SI (reg:SI T_REG)
 			 (match_operand:SI 1 "arith_reg_operand" "r"))))
-   (set (reg:SI 18)
-	(ne:SI (ior:SI (reg:SI 18) (match_dup 1))
+   (set (reg:SI T_REG)
+	(ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
 	       (const_int 0)))]
   ""
   "negc	%1,%0"
@@ -2118,7 +2164,7 @@
 (define_expand "negdi2"
   [(set (match_operand:DI 0 "arith_reg_operand" "")
 	(neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
-   (clobber (reg:SI 18))]
+   (clobber (reg:SI T_REG))]
   ""
   "
 {
@@ -2220,27 +2266,27 @@
 ;; define push and pop so it is easy for sh.c
 
 (define_expand "push"
-  [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+  [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
 	(match_operand:SI 0 "register_operand" "r,l,x"))]
   ""
   "")
 
 (define_expand "pop"
   [(set (match_operand:SI 0 "register_operand" "=r,l,x")
-	(mem:SI (post_inc:SI (reg:SI 15))))]
+	(mem:SI (post_inc:SI (reg:SI SP_REG))))]
   ""
   "")
 
 (define_expand "push_e"
-  [(parallel [(set (mem:SF (pre_dec:SI (reg:SI 15)))
+  [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
 		   (match_operand:SF 0 "" ""))
-	      (use (reg:PSI 48))
+	      (use (reg:PSI FPSCR_REG))
 	      (clobber (scratch:SI))])]
   ""
   "")
 
 (define_insn "push_fpul"
-  [(set (mem:SF (pre_dec:SI (reg:SI 15))) (reg:SF 22))]
+  [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
   "TARGET_SH3E"
   "sts.l	fpul,@-r15"
   [(set_attr "type" "store")
@@ -2249,22 +2295,22 @@
 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
 ;; so use that.
 (define_expand "push_4"
-  [(parallel [(set (mem:DF (pre_dec:SI (reg:SI 15))) (match_operand:DF 0 "" ""))
-	      (use (reg:PSI 48))
+  [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG))) (match_operand:DF 0 "" ""))
+	      (use (reg:PSI FPSCR_REG))
 	      (clobber (scratch:SI))])]
   ""
   "")
 
 (define_expand "pop_e"
   [(parallel [(set (match_operand:SF 0 "" "")
-	      (mem:SF (post_inc:SI (reg:SI 15))))
-	      (use (reg:PSI 48))
+	      (mem:SF (post_inc:SI (reg:SI SP_REG))))
+	      (use (reg:PSI FPSCR_REG))
 	      (clobber (scratch:SI))])]
   ""
   "")
 
 (define_insn "pop_fpul"
-  [(set (reg:SF 22) (mem:SF (post_inc:SI (reg:SI 15))))]
+  [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
   "TARGET_SH3E"
   "lds.l	@r15+,fpul"
   [(set_attr "type" "load")
@@ -2272,8 +2318,8 @@
 
 (define_expand "pop_4"
   [(parallel [(set (match_operand:DF 0 "" "")
-		   (mem:DF (post_inc:SI (reg:SI 15))))
-	      (use (reg:PSI 48))
+		   (mem:DF (post_inc:SI (reg:SI SP_REG))))
+	      (use (reg:PSI FPSCR_REG))
 	      (clobber (scratch:SI))])]
   ""
   "")
@@ -2283,17 +2329,17 @@
 ;; They don't disappear completely, because the T reg is a fixed hard reg.
 
 (define_insn "clrt"
-  [(set (reg:SI 18) (const_int 0))]
+  [(set (reg:SI T_REG) (const_int 0))]
   ""
   "clrt")
 
 (define_insn "sett"
-  [(set (reg:SI 18) (const_int 1))]
+  [(set (reg:SI T_REG) (const_int 1))]
   ""
   "sett")
 
 ;; t/r must come after r/r, lest reload will try to reload stuff like
-;; (set (subreg:SI (mem:QI (plus:SI (reg:SI 15 r15) (const_int 12)) 0) 0)
+;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
 ;; (made from (set (subreg:SI (reg:QI 73) 0) ) into T.
 (define_insn "movsi_i"
   [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,r")
@@ -2650,7 +2696,7 @@
   [(set (match_operand:DF 0 "register_operand" "")
 	(match_operand:DF 1 "memory_operand"  ""))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (reg:SI 0))]
+   (clobber (reg:SI R0_REG))]
   "TARGET_SH4 && reload_completed"
   [(parallel [(set (match_dup 0) (match_dup 1))
 	      (use (match_dup 2))
@@ -2660,7 +2706,7 @@
 (define_expand "reload_indf"
   [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
 		   (match_operand:DF 1 "immediate_operand" "FQ"))
-	      (use (reg:PSI 48))
+	      (use (reg:PSI FPSCR_REG))
 	      (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
   ""
   "")
@@ -2822,7 +2868,7 @@
 ;; won't get a bogus tertiary reload.
 ;; We use tertiary_reload_operand instead of memory_operand here because
 ;; memory_operand rejects operands that are not directly addressible, e.g.:
-;; (mem:SF (plus:SI (reg:SI 14 r14)
+;; (mem:SF (plus:SI (reg:SI FRP_REG)
 ;;         (const_int 132)))
 
 (define_expand "reload_outsf"
@@ -2890,7 +2936,7 @@
 	(match_operand:SI 1 "" ""))
    (clobber (match_operand 2 "register_operand" ""))]
   "! reload_in_progress && ! reload_completed"
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "
 {
   rtx addr, reg, const_int;
@@ -2917,7 +2963,7 @@
 	(match_operand:SI 0 "register_operand" ""))
    (clobber (match_operand 2 "register_operand" ""))]
   "! reload_in_progress && ! reload_completed"
-  [(use (reg:SI 0))]
+  [(use (reg:SI R0_REG))]
   "
 {
   rtx addr, reg, const_int;
@@ -3015,12 +3061,12 @@
   [(set (match_operand:SF 0 "register_operand" "")
 	(match_operand:SF 1 "register_operand" ""))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))
-   (clobber (reg:SI 22))]
+   (clobber (reg:SI FPUL_REG))]
   ""
-  [(parallel [(set (reg:SF 22) (match_dup 1))
+  [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
 	      (use (match_dup 2))
 	      (clobber (scratch:SI))])
-   (parallel [(set (match_dup 0) (reg:SF 22))
+   (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
 	      (use (match_dup 2))
 	      (clobber (scratch:SI))])]
   "")
@@ -3050,7 +3096,7 @@
 (define_expand "reload_insf"
   [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
 		   (match_operand:SF 1 "immediate_operand" "FQ"))
-	      (use (reg:PSI 48))
+	      (use (reg:PSI FPSCR_REG))
 	      (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
   ""
   "")
@@ -3084,7 +3130,7 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_operand:SI 1 "memory_operand" ""))
-   (clobber (reg:SI 0))]
+   (clobber (reg:SI R0_REG))]
   ""
   [(set (match_dup 0) (match_dup 1))]
   "")
@@ -3094,7 +3140,7 @@
 ;; ------------------------------------------------------------------------
 
 (define_insn "branch_true"
-  [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 0))
+  [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
 			   (label_ref (match_operand 0 "" ""))
 			   (pc)))]
   ""
@@ -3102,7 +3148,7 @@
   [(set_attr "type" "cbranch")])
 
 (define_insn "branch_false"
-  [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 0))
+  [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
 			   (label_ref (match_operand 0 "" ""))
 			   (pc)))]
   ""
@@ -3132,7 +3178,7 @@
 
 (define_expand "beq"
   [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
+	(if_then_else (ne (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3140,7 +3186,7 @@
 
 (define_expand "bne"
   [(set (pc)
-	(if_then_else (eq (reg:SI 18) (const_int 0))
+	(if_then_else (eq (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3148,7 +3194,7 @@
 
 (define_expand "bgt"
   [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
+	(if_then_else (ne (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3156,7 +3202,7 @@
 
 (define_expand "blt"
   [(set (pc)
-	(if_then_else (eq (reg:SI 18) (const_int 0))
+	(if_then_else (eq (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3175,7 +3221,7 @@
 
 (define_expand "ble"
   [(set (pc)
-	(if_then_else (eq (reg:SI 18) (const_int 0))
+	(if_then_else (eq (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3196,7 +3242,7 @@
 
 (define_expand "bge"
   [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
+	(if_then_else (ne (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3217,7 +3263,7 @@
 
 (define_expand "bgtu"
   [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
+	(if_then_else (ne (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3225,15 +3271,15 @@
 
 (define_expand "bltu"
   [(set (pc)
-		  (if_then_else (eq (reg:SI 18) (const_int 0))
-				(label_ref (match_operand 0 "" ""))
-				(pc)))]
+	(if_then_else (eq (reg:SI T_REG) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
   ""
   "from_compare (operands, GEU);")
 
 (define_expand "bgeu"
   [(set (pc)
-	(if_then_else (ne (reg:SI 18) (const_int 0))
+	(if_then_else (ne (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3241,7 +3287,7 @@
 
 (define_expand "bleu"
   [(set (pc)
-	(if_then_else (eq (reg:SI 18) (const_int 0))
+	(if_then_else (eq (reg:SI T_REG) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
@@ -3269,8 +3315,8 @@
 (define_insn "calli"
   [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
 	 (match_operand 1 "" ""))
-   (use (reg:SI 48))
-   (clobber (reg:SI 17))]
+   (use (reg:PSI FPSCR_REG))
+   (clobber (reg:SI PR_REG))]
   ""
   "jsr	@%0%#"
   [(set_attr "type" "call")
@@ -3284,9 +3330,9 @@
 (define_insn "calli_pcrel"
   [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
 	 (match_operand 1 "" ""))
-   (use (reg:SI 48))
+   (use (reg:PSI FPSCR_REG))
    (use (match_operand 2 "" ""))
-   (clobber (reg:SI 17))]
+   (clobber (reg:SI PR_REG))]
   "TARGET_SH2"
   "bsrf	%0\\n%O2:%#"
   [(set_attr "type" "call")
@@ -3299,8 +3345,8 @@
   [(set (match_operand 0 "" "=rf")
 	(call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
 	      (match_operand 2 "" "")))
-   (use (reg:SI 48))
-   (clobber (reg:SI 17))]
+   (use (reg:PSI FPSCR_REG))
+   (clobber (reg:SI PR_REG))]
   ""
   "jsr	@%1%#"
   [(set_attr "type" "call")
@@ -3313,9 +3359,9 @@
   [(set (match_operand 0 "" "=rf")
 	(call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
 	      (match_operand 2 "" "")))
-   (use (reg:SI 48))
+   (use (reg:PSI FPSCR_REG))
    (use (match_operand 3 "" ""))
-   (clobber (reg:SI 17))]
+   (clobber (reg:SI PR_REG))]
   "TARGET_SH2"
   "bsrf	%1\\n%O3:%#"
   [(set_attr "type" "call")
@@ -3327,8 +3373,8 @@
 (define_expand "call"
   [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
 			    (match_operand 1 "" ""))
-	      (use (reg:SI 48))
-	      (clobber (reg:SI 17))])]
+	      (use (reg:PSI FPSCR_REG))
+	      (clobber (reg:SI PR_REG))])]
   ""
   "
 {
@@ -3354,8 +3400,8 @@
   [(parallel [(set (match_operand 0 "arith_reg_operand" "")
 		   (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
 				 (match_operand 2 "" "")))
-	      (use (reg:SI 48))
-	      (clobber (reg:SI 17))])]
+	      (use (reg:PSI FPSCR_REG))
+	      (clobber (reg:SI PR_REG))])]
   ""
   "
 {
@@ -3445,7 +3491,7 @@
 ;; ------------------------------------------------------------------------
 
 (define_insn "dect"
-  [(set (reg:SI 18)
+  [(set (reg:SI T_REG)
 	(eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
    (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
   "TARGET_SH2"
@@ -3463,7 +3509,7 @@
 ;; within range,
 
 (define_insn "mova"
-  [(set (reg:SI 0)
+  [(set (reg:SI R0_REG)
 	(unspec [(label_ref (match_operand 0 "" ""))] 1))]
   ""
   "mova	%O0,r0"
@@ -3471,9 +3517,10 @@
    (set_attr "type" "arith")])
 
 (define_expand "GOTaddr2picreg"
-  [(set (reg:SI 0) (const (unspec [(const (unspec [(match_dup 1)] 6))] 1)))
+  [(set (reg:SI R0_REG)
+	(const (unspec [(const (unspec [(match_dup 1)] 6))] 1)))
   (set (match_dup 0) (const (unspec [(match_dup 1)] 6)))
-  (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
+  (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
   "" "
 {
   operands[0] = pic_offset_table_rtx;
@@ -3581,11 +3628,11 @@
   [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
    (set (match_dup 4) (minus:SI (match_dup 4)
 				(match_operand:SI 1 "arith_operand" "")))
-   (set (reg:SI 18)
+   (set (reg:SI T_REG)
 	(gtu:SI (match_dup 4)
 		(match_operand:SI 2 "arith_reg_operand" "")))
    (set (pc)
-	(if_then_else (ne (reg:SI 18)
+	(if_then_else (ne (reg:SI T_REG)
 			  (const_int 0))
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
@@ -3612,11 +3659,12 @@
    (clobber (match_scratch:SI 3 ""))
    (clobber (match_scratch:SI 4 ""))]
   "! TARGET_SH2 && reload_completed"
-  [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
+  [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] 1))
    (parallel [(set (match_dup 0)
-	      (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
+	      (unspec [(reg:SI R0_REG) (match_dup 1)
+		        (label_ref (match_dup 2))] 2))
 	      (clobber (match_dup 3))])
-   (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
+   (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
   "LABEL_NUSES (operands[2])++;")
 
 (define_split
@@ -3626,15 +3674,16 @@
    (clobber (match_scratch:SI 3 ""))
    (clobber (match_scratch:SI 4 ""))]
   "TARGET_SH2 && reload_completed"
-  [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
+  [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] 1))
    (parallel [(set (match_dup 0)
-	      (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
+	      (unspec [(reg:SI R0_REG) (match_dup 1)
+		       (label_ref (match_dup 2))] 2))
 	      (clobber (match_dup 3))])]
   "LABEL_NUSES (operands[2])++;")
 
 (define_insn "*casesi_worker"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(unspec [(reg:SI 0) (match_operand 1 "register_operand" "0,r")
+	(unspec [(reg:SI R0_REG) (match_operand 1 "register_operand" "0,r")
 		 (label_ref (match_operand 2 "" ""))] 2))
    (clobber (match_scratch:SI 3 "=X,1"))]
   ""
@@ -3695,7 +3744,7 @@
 
 (define_insn "movt"
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
-	(eq:SI (reg:SI 18) (const_int 1)))]
+	(eq:SI (reg:SI T_REG) (const_int 1)))]
   ""
   "movt	%0"
   [(set_attr "type" "arith")])
@@ -3791,7 +3840,7 @@
    (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
 		   (neg:SI (plus:SI (match_dup 1)
 				    (match_dup 2))))
-	      (set (reg:SI 18)
+	      (set (reg:SI T_REG)
 		   (ne:SI (ior:SI (match_dup 1) (match_dup 2))
 			  (const_int 0)))])]  
   ""
@@ -3807,7 +3856,7 @@
    (parallel [(set (match_operand 0 "" "")
 		   (neg:SI (plus:SI (match_dup 1)
 				    (match_dup 2))))
-	      (set (reg:SI 18)
+	      (set (reg:SI T_REG)
 		   (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
 			  (const_int 0)))])]  
   ""
@@ -3819,10 +3868,10 @@
 
 (define_split
   [(set (match_operand:SI 0 "arith_reg_operand" "")
-	(plus:SI (reg:SI 18)
+	(plus:SI (reg:SI T_REG)
 		 (const_int -1)))]
   ""
-  [(set (match_dup 0) (eq:SI (reg:SI 18) (const_int 1)))
+  [(set (match_dup 0) (eq:SI (reg:SI T_REG) (const_int 1)))
    (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
   "")
 
@@ -3950,10 +3999,10 @@
 		   (mem:BLK (match_operand:BLK 1 "" "")))
 	      (use (match_operand:SI 2 "nonmemory_operand" ""))
 	      (use (match_operand:SI 3 "immediate_operand" ""))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 4))
-	      (clobber (reg:SI 5))
-	      (clobber (reg:SI 0))])]
+	      (clobber (reg:SI PR_REG))
+	      (clobber (reg:SI R4_REG))
+	      (clobber (reg:SI R5_REG))
+	      (clobber (reg:SI R0_REG))])]
   ""
   "
 {
@@ -3963,59 +4012,59 @@
 }")
 
 (define_insn "block_move_real"
-  [(parallel [(set (mem:BLK (reg:SI 4))
-		   (mem:BLK (reg:SI 5)))
+  [(parallel [(set (mem:BLK (reg:SI R4_REG))
+		   (mem:BLK (reg:SI R5_REG)))
 	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 0))])]
+	      (clobber (reg:SI PR_REG))
+	      (clobber (reg:SI R0_REG))])]
   "! TARGET_HARD_SH4"
   "jsr	@%0%#"
   [(set_attr "type" "sfunc")
    (set_attr "needs_delay_slot" "yes")])
 
 (define_insn "block_lump_real"
-  [(parallel [(set (mem:BLK (reg:SI 4))
-		   (mem:BLK (reg:SI 5)))
+  [(parallel [(set (mem:BLK (reg:SI R4_REG))
+		   (mem:BLK (reg:SI R5_REG)))
 	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
-	      (use (reg:SI 6))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 18))
-	      (clobber (reg:SI 4))
-	      (clobber (reg:SI 5))
-	      (clobber (reg:SI 6))
-	      (clobber (reg:SI 0))])]
+	      (use (reg:SI R6_REG))
+	      (clobber (reg:SI PR_REG))
+	      (clobber (reg:SI T_REG))
+	      (clobber (reg:SI R4_REG))
+	      (clobber (reg:SI R5_REG))
+	      (clobber (reg:SI R6_REG))
+	      (clobber (reg:SI R0_REG))])]
   "! TARGET_HARD_SH4"
   "jsr	@%0%#"
   [(set_attr "type" "sfunc")
    (set_attr "needs_delay_slot" "yes")])
 
 (define_insn "block_move_real_i4"
-  [(parallel [(set (mem:BLK (reg:SI 4))
-		   (mem:BLK (reg:SI 5)))
+  [(parallel [(set (mem:BLK (reg:SI R4_REG))
+		   (mem:BLK (reg:SI R5_REG)))
 	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 1))
-	      (clobber (reg:SI 2))])]
+	      (clobber (reg:SI PR_REG))
+	      (clobber (reg:SI R0_REG))
+	      (clobber (reg:SI R1_REG))
+	      (clobber (reg:SI R2_REG))])]
   "TARGET_HARD_SH4"
   "jsr	@%0%#"
   [(set_attr "type" "sfunc")
    (set_attr "needs_delay_slot" "yes")])
 
 (define_insn "block_lump_real_i4"
-  [(parallel [(set (mem:BLK (reg:SI 4))
-		   (mem:BLK (reg:SI 5)))
+  [(parallel [(set (mem:BLK (reg:SI R4_REG))
+		   (mem:BLK (reg:SI R5_REG)))
 	      (use (match_operand:SI 0 "arith_reg_operand" "r"))
-	      (use (reg:SI 6))
-	      (clobber (reg:SI 17))
-	      (clobber (reg:SI 18))
-	      (clobber (reg:SI 4))
-	      (clobber (reg:SI 5))
-	      (clobber (reg:SI 6))
-	      (clobber (reg:SI 0))
-	      (clobber (reg:SI 1))
-	      (clobber (reg:SI 2))
-	      (clobber (reg:SI 3))])]
+	      (use (reg:SI R6_REG))
+	      (clobber (reg:SI PR_REG))
+	      (clobber (reg:SI T_REG))
+	      (clobber (reg:SI R4_REG))
+	      (clobber (reg:SI R5_REG))
+	      (clobber (reg:SI R6_REG))
+	      (clobber (reg:SI R0_REG))
+	      (clobber (reg:SI R1_REG))
+	      (clobber (reg:SI R2_REG))
+	      (clobber (reg:SI R3_REG))])]
   "TARGET_HARD_SH4"
   "jsr	@%0%#"
   [(set_attr "type" "sfunc")
@@ -4087,7 +4136,8 @@
    (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
 
 (define_split
-  [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
+  [(set (reg:PSI FPSCR_REG)
+	(mem:PSI (match_operand:SI 0 "register_operand" "r")))]
   "find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
   [(set (match_dup 0) (match_dup 0))]
   "
@@ -4100,7 +4150,8 @@
 }")
 
 (define_split
-  [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
+  [(set (reg:PSI FPSCR_REG)
+	(mem:PSI (match_operand:SI 0 "register_operand" "r")))]
   ""
   [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
   "
@@ -4119,7 +4170,8 @@
 ;; it is probably best to claim no function unit, which matches the
 ;; current setting.
 (define_insn "toggle_sz"
-  [(set (reg:PSI 48) (xor:PSI (reg:PSI 48) (const_int 1048576)))]
+  [(set (reg:PSI FPSCR_REG)
+	(xor:PSI (reg:PSI FPSCR_REG) (const_int 1048576)))]
   "TARGET_SH4"
   "fschg")
 
@@ -4278,8 +4330,8 @@
 ;; (define_insn "fix_truncsfsi2_i4_2"
 ;;  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 ;;	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
-;;   (use (reg:SI 48))
-;;   (clobber (reg:SI 22))]
+;;   (use (reg:PSI FPSCR_REG))
+;;   (clobber (reg:SI FPUL_REG))]
 ;;  "TARGET_SH4"
 ;;  "#"
 ;;  [(set_attr "length" "4")
@@ -4289,11 +4341,11 @@
 ;;  [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 ;;	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
 ;;   (use (match_operand:PSI 2 "fpscr_operand" "c"))
-;;   (clobber (reg:SI 22))]
+;;   (clobber (reg:SI FPUL_REG))]
 ;;  "TARGET_SH4"
-;;  [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
+;;  [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
 ;;	      (use (match_dup 2))])
-;;   (set (match_dup 0) (reg:SI 22))])
+;;   (set (match_dup 0) (reg:SI FPUL_REG))])
 
 (define_insn "*fixsfsi"
   [(set (match_operand:SI 0 "fpul_operand" "=y")
@@ -4303,7 +4355,7 @@
   [(set_attr "type" "fp")])
 
 (define_insn "cmpgtsf_t"
-  [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+  [(set (reg:SI T_REG) (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
 			   (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
   "TARGET_SH3E && ! TARGET_SH4"
   "fcmp/gt	%1,%0"
@@ -4311,7 +4363,7 @@
    (set_attr "fp_mode" "single")])
 
 (define_insn "cmpeqsf_t"
-  [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+  [(set (reg:SI T_REG) (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
 			   (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
   "TARGET_SH3E && ! TARGET_SH4"
   "fcmp/eq	%1,%0"
@@ -4319,8 +4371,8 @@
    (set_attr "fp_mode" "single")])
 
 (define_insn "ieee_ccmpeqsf_t"
-  [(set (reg:SI 18)
-	(ior:SI (reg:SI 18)
+  [(set (reg:SI T_REG)
+	(ior:SI (reg:SI T_REG)
 		(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
 		       (match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
   "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
@@ -4329,8 +4381,9 @@
 
 
 (define_insn "cmpgtsf_t_i4"
-  [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
-			   (match_operand:SF 1 "fp_arith_reg_operand" "f")))
+  [(set (reg:SI T_REG)
+	(gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+	       (match_operand:SF 1 "fp_arith_reg_operand" "f")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
   "fcmp/gt	%1,%0"
@@ -4338,8 +4391,9 @@
    (set_attr "fp_mode" "single")])
 
 (define_insn "cmpeqsf_t_i4"
-  [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
-			   (match_operand:SF 1 "fp_arith_reg_operand" "f")))
+  [(set (reg:SI T_REG)
+	(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
+	       (match_operand:SF 1 "fp_arith_reg_operand" "f")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
   "fcmp/eq	%1,%0"
@@ -4347,8 +4401,8 @@
    (set_attr "fp_mode" "single")])
 
 (define_insn "*ieee_ccmpeqsf_t_4"
-  [(set (reg:SI 18)
-	(ior:SI (reg:SI 18)
+  [(set (reg:SI T_REG)
+	(ior:SI (reg:SI T_REG)
 		(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
 		       (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
@@ -4358,8 +4412,9 @@
    (set_attr "fp_mode" "single")])
 
 (define_expand "cmpsf"
-  [(set (reg:SI 18) (compare (match_operand:SF 0 "arith_operand" "")
-			     (match_operand:SF 1 "arith_operand" "")))]
+  [(set (reg:SI T_REG)
+	(compare (match_operand:SF 0 "arith_operand" "")
+		 (match_operand:SF 1 "arith_operand" "")))]
   "TARGET_SH3E"
   "
 {
@@ -4525,7 +4580,7 @@
 ;;   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 ;; 	(fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
 ;;    (use (match_operand:PSI 2 "fpscr_operand" "c"))
-;;    (clobber (reg:SI 22))]
+;;    (clobber (reg:SI FPUL_REG))]
 ;;   "TARGET_SH4"
 ;;   "#"
 ;;   [(set_attr "length" "4")
@@ -4535,15 +4590,16 @@
 ;;   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 ;; 	(fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
 ;;    (use (match_operand:PSI 2 "fpscr_operand" "c"))
-;;    (clobber (reg:SI 22))]
+;;    (clobber (reg:SI FPUL_REG))]
 ;;   "TARGET_SH4"
-;;   [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
+;;   [(parallel [(set (reg:SI FPUL_REG) (fix:SI (match_dup 1)))
 ;; 	      (use (match_dup 2))])
-;;    (set (match_dup 0) (reg:SI 22))])
+;;    (set (match_dup 0) (reg:SI FPUL_REG))])
 
 (define_insn "cmpgtdf_t"
-  [(set (reg:SI 18) (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
-			   (match_operand:DF 1 "arith_reg_operand" "f")))
+  [(set (reg:SI T_REG)
+	(gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
+	       (match_operand:DF 1 "arith_reg_operand" "f")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
   "fcmp/gt	%1,%0"
@@ -4551,8 +4607,9 @@
    (set_attr "fp_mode" "double")])
 
 (define_insn "cmpeqdf_t"
-  [(set (reg:SI 18) (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
-			   (match_operand:DF 1 "arith_reg_operand" "f")))
+  [(set (reg:SI T_REG)
+	(eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
+	       (match_operand:DF 1 "arith_reg_operand" "f")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
   "fcmp/eq	%1,%0"
@@ -4560,9 +4617,10 @@
    (set_attr "fp_mode" "double")])
 
 (define_insn "*ieee_ccmpeqdf_t"
-  [(set (reg:SI 18) (ior:SI (reg:SI 18)
-			    (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
-				   (match_operand:DF 1 "arith_reg_operand" "f"))))
+  [(set (reg:SI T_REG)
+	(ior:SI (reg:SI T_REG)
+		(eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
+		       (match_operand:DF 1 "arith_reg_operand" "f"))))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_IEEE && TARGET_SH4"
   "* return output_ieee_ccmpeq (insn, operands);"
@@ -4570,8 +4628,9 @@
    (set_attr "fp_mode" "double")])
    
 (define_expand "cmpdf"
-  [(set (reg:SI 18) (compare (match_operand:DF 0 "arith_operand" "")
-			     (match_operand:DF 1 "arith_operand" "")))]
+  [(set (reg:SI T_REG)
+	(compare (match_operand:DF 0 "arith_operand" "")
+		 (match_operand:DF 1 "arith_operand" "")))]
   "TARGET_SH4"
   "
 {
@@ -4730,7 +4789,7 @@
   [(set (match_operand:SI 0 "arith_reg_operand" "=r")
 	(plus:SI (match_dup 0)
 		 (const_int -1)))
-   (set (reg:SI 18)
+   (set (reg:SI T_REG)
 	(eq:SI (match_dup 0)
 	       (const_int 0)))]
   "TARGET_SH2"
Index: gcc/config/sh/t-sh
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sh/t-sh,v
retrieving revision 1.8
diff -u -p -r1.8 t-sh
--- gcc/config/sh/t-sh 2000/09/14 20:31:01 1.8
+++ gcc/config/sh/t-sh 2000/11/16 09:05:42
@@ -1,3 +1,22 @@
+# sh.md is ``preprocessed'' with a sed script derived from sh-md.h.
+md_file = md
+
+md-sed: $(srcdir)/config/sh/sh-md.h
+	-rm -f $@ tmp-$@
+	sed -n 's/^#[ 	]*define[ 	][ 	]*\([A-Z_][A-Z0-9_]*\)[ 	][ 	]*\([0-9][0-9]*\)[ 	]*/s,\1,\2,g/p' \
+	  < $(srcdir)/config/sh/sh-md.h > tmp-$@
+	mv tmp-$@ $@
+	
+md: $(srcdir)/config/sh/sh.md md-sed
+	-rm -f $@ $@
+	sed -f md-sed < $(srcdir)/config/sh/sh.md > tmp-$@
+	mv tmp-$@ $@
+
+clean: sh-clean
+sh-clean:
+	-rm -f md md-sed
+
+
 CROSS_LIBGCC1 = libgcc1-asm.a
 LIB1ASMSRC = sh/lib1funcs.asm
 LIB1ASMFUNCS = _ashiftrt _ashiftrt_n _ashiftlt _lshiftrt _movstr \

-- 
Alexandre Oliva   Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer                  aoliva@{cygnus.com, redhat.com}
CS PhD student at IC-Unicamp        oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist    *Please* write to mailing lists, not to me

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