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Re: Support for ARM interrupt handler functions. said:
>   I have created a patch to add support for an "interrupt" function
>   attribute for the ARM port.  I would like to check it in, but I
>   wanted to see if you (or anyone else) had any comments or
>   reservations first.

Great; we've needed this for a while.

>   Interrupt handler functions are basically just the same as normal
>   functions except that they have an exit instruction of:
>         subs pc, lr, #4
>   I also disable sibcall and tailcall optimisations for these
>   functions.  Note at the request of Intel, who originally asked for
>   this work, the attribute can also be called "irq".

Seems ok.

>   As well as adding support for the attribute, the patch also tidies
>   up the prologue and epilogue generation code somewhat, so that now
>   there is a single function which computes which registers needs to
>   be saved in the prologue and restored in the epilogue.  This
>   function is then called from all of the places that used to perform 
>   these calculations individually.

A sound move; it's been something on my todo list for a while.

>   Note - I have tried to make sure that the patch does not break any
>   of the exception handling code, but it is hard to know if I got this
>   right.  It seems that exception handling for the ARM is not really
>   working at the moment.  Certainly there are lots of failures in the
>   G++ testsuite.   But I think that my patch does not introduce any
>   new bugs.

Dwarf exceptions have been broken ever since Jason "fixed" the code.  I 
haven't had a chance to look into why.

I would like to have a closer look at the code before it goes in; but I've 
been off all week (holiday) and I'm going to be away for most of the next 
two weeks (trip to your side of the planet).  I'll see if I can squeeze it 
in before I go.


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