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Re: cr logical insn implementation for rs6000

> cc:
> Date: Wed, 06 Sep 2000 16:19:31 -0400
> From: David Edelsohn <>
> >>>>> Geoff Keating writes:
> Geoff> They're execute-synchronized according to the docs on the 604 and 750.
> Geoff> I expect that they will usually have a latency of 3-4 cycles, as it'll
> Geoff> take 2-3 cycles for the pipeline to flush.  There doesn't seem to be
> Geoff> an easy way to explain execute-synchronization to the old scheduler,
> Geoff> and I'm unwilling to spend much time on it when it'll all go away RSN
> Geoff> with the DFA-based pipeline descriptions.
> 	The execution serialization of those instructions on the 604 and
> 750 cannot be generalized.  On the processors with a separate CR Logic
> Unit, they are not serialized -- only those where they are in the Branch
> Unit have the serialization.  I will fix this as well.
> 	What is the new DFA-based pipeline scheduler?

It's a more accurate way of describing instruction timings.  It can
cope with things like function unit dependencies, limits on
instruction dispatch and/or completion, and so on.  Of course, it
needs much more detailed information than the current scheduling model
to be done right.

> Geoff> If you happen to have a POWER3 data book handy, one that describes the
> Geoff> instruction timings in detail, that'd be very useful.  Especially in
> Geoff> PDF form...
> 	Unfortunately, the documents are IBM Confidential.  I work across
> the hall from the person who maintains the documents for all IBM PowerPC
> architectures, so it is easy for me to look up any details for any IBM
> chip implementation.

Hmmm.  I probably couldn't use it then anyway.  I'll leave the
scheduling for the IBM-specific chips to you then, as you're best
placed to deal with IBM confidentiality rules.

- Geoffrey Keating <>

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