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Re: cr logical insn implementation for rs6000


David Edelsohn <dje@watson.ibm.com> writes:

> 	Given this recent change, I would like to refer back to my
> proposed patch of about a month ago cleaning up some of the sCOND
> patterns.  As far as I can tell, some of the patterns are better done by
> GCC's portable code, especially when not on the POWER architecture.

The patch looks good.  Anything that saves me from having to rewrite
those patterns :-).

> 	Also, the function unit information has a number of errors
> following the addition of cr_logical attribute.  I also do not understand
> why cr_logical instructions are assigned a latency of 4 cycles when they
> all operate in 1 cycle.

They're execute-synchronized according to the docs on the 604 and 750.
I expect that they will usually have a latency of 3-4 cycles, as it'll
take 2-3 cycles for the pipeline to flush.  There doesn't seem to be
an easy way to explain execute-synchronization to the old scheduler,
and I'm unwilling to spend much time on it when it'll all go away RSN
with the DFA-based pipeline descriptions.

> 	My patch below contains both the sCOND improvements and the cr
> logical instruction unit rearrangement, but I did not change the latency
> information until I hear whether 4 cycles was a typo or intended.
> 
> Thanks, David
> 
> 	P.S. Geoff, in the future, please contact me for function unit
> information.

If you happen to have a POWER3 data book handy, one that describes the
instruction timings in detail, that'd be very useful.  Especially in
PDF form...

-- 
- Geoffrey Keating <geoffk@cygnus.com>

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