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Re: P3 SSE/MMX support: adding the patterns
On Tue, Sep 05, 2000 at 05:00:49PM +0100, Bernd Schmidt wrote:
> @@ -1535,6 +1553,9 @@
> "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
> "*
> {
> + if (MMX_REG_P (operands[0]) || MMX_REG_P (operands[1]))
> + return \"movd\\t{%1, %0|%0, %1}\";
> +
> switch (get_attr_type (insn))
> {
> case TYPE_LEA:
I'd really prefer this be inside the switch statement. This will
force you to get the scheduling types correct.
> (define_insn "*movdi_2"
> - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
> - (match_operand:DI 1 "general_operand" "riFo,riF"))]
> + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y")
> + (match_operand:DI 1 "general_operand" "riFo,riF,*y,m"))]
> "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
> - "#")
> + "@
> + #
> + #
> + movq\\t{%1, %0|%0, %1}
> + movq\\t{%1, %0|%0, %1}")
Need to add scheduling types for the non-split alternatives.
> + && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
> + && operands[1] != CONST0_RTX (TImode))
There's no need for the first clause. Constants are unique.
> +(define_insn_and_split "*pushti"
> + [(set (match_operand:TI 0 "push_operand" "=<")
> + (match_operand:TI 1 "nonmemory_operand" "x"))]
> + "TARGET_SSE"
> + "#"
> + ""
> + [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
> + (set (mem:TI (reg:SI 7)) (match_dup 1))]
> + "")
Perhaps we ought to make calls.c generate these? Seems silly to
have to define nine variants of the same thing.
> +(define_insn "sse_movhps"
> + [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
> + (vec_merge:V4SF
> + (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
> + (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
> + (const_int 12)))]
> + "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
> + "movhps\\t{%2, %0|%0, %2}")
For normal named patterns it is illegal to refer to its operands
in the extra_c_test. Normally you'd have an expander that fixed
things up to make sure you matched. Is there something elsewhere
that makes sure that things are correct?
> +(define_insn "sse_comi"
> + [(set (reg:CC 17)
> + (match_operator:CC 2 "sse_comparison_operator"
> +
> +(define_insn "sse_ucomi"
> + [(set (reg:CC 17)
> + (unspec:CC
> + [(match_operator 2 "sse_comparison_operator"
Why not use CCFP and CCFPU modes to distinguish these instead
of an unspec?
> +(define_insn "sfence"
> + [(unspec_volatile [(const_int 0)] 44)]
> + "TARGET_SSE"
> + "sfence")
You only need to prevent movement of memories across the insn.
You might consider a definition like that for "mf" for ia64.
> +(define_insn "prefetch"
> + [(unspec_volatile [(match_operand:SI 0 "address_operand" "p")
> + (match_operand:SI 1 "address_operand" "p")] 35)]
Should just be unspec, not unspec_volatile. No need to prevent
scheduling across it.
r~