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Mark option/switch description for translation
- To: gcc-patches at gcc dot gnu dot org
- Subject: Mark option/switch description for translation
- From: Philipp Thomas <pthomas at suse dot de>
- Date: Mon, 26 Jun 2000 06:09:37 +0200
- Cc: Mark Mitchell <mark at codesourcery dot com>
These patches mark the description strings in various target headers as
strings to be translated. I tested some of them by building cc1, though not
all. OK to install?
2000-06-26 Philipp Thomas <pthomas@suse.de>
* 1750a.h: Mark help strings for options/switches for translation.
* a29k.h: Likewise.
* alpha.h: Likewise.
* arm.h: Likewise.
* pe.h: Likewise.
* riscix.h: Likewise.
* c4x.h: Likewise.
* clipper.h: Likewise.
* convex.h: Likewise.
* elxsi.h: Likewise.
* fr30.h: Likewise.
* fx80.h: Likewise.
* h8300.h: Likewise.
* i370.h: Likewise.
* cygwin.h: Likewise.
* dgux.h: Likewise.
* djgpp.h: Likewise.
* i386.h: Likewise.
* osf1elf.h: Likewise.
* osfrose.h: Likewise.
* sco5.h: Likewise.
* win32.h: Likewise.
* i860.h: Likewise.
* paragon.h: Likewise.
* i960.h: Likewise.
* ia64.h: Likewise.
* m32r.h: Likewise.
* mcore.h: Likewise.
* mips.h: Likewise.
* mn10300.h: Likewise.
* ns32k.h: Likewise.
* pdp11.h: Likewise.
* pj.h: Likewise.
* aix.h: Likewise.
* aix41.h: Likewise.
* aix43.h: Likewise.
* beos.h: Likewise.
* rs6000.h: Likewise.
* sysv4.h: Likewise.
* linux.h: Likewise.
* linux64.h: Likewise.
* sp64-elf.h: Likewise.
* sparc.h: Likewise.
* splet.h: Likewise.
* v850.h: Likewise.
* convex.h (TARGET_SWITCHES): Provide descriptions and mark them
for translation.
Index: config/1750a/1750a.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/1750a/1750a.h,v
retrieving revision 1.18
diff -u -p -r1.18 1750a.h
--- 1750a.h 2000/05/01 17:17:55 1.18
+++ 1750a.h 2000/06/26 03:41:14
@@ -35,8 +35,8 @@ Boston, MA 02111-1307, USA. */
/* Run-time compilation parameters selecting different hardware subsets. */
-#define TARGET_SWITCHES \
- { {"vaxc-alignment", 2, "Use VAX-C alignment"}, \
+#define TARGET_SWITCHES \
+ { {"vaxc-alignment", 2, N_("Use VAX-C alignment")}, \
{ "", TARGET_DEFAULT, NULL}}
/* Default target_flags if no switches specified. */
Index: config/a29k/a29k.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/a29k/a29k.h,v
retrieving revision 1.14
diff -u -p -r1.14 a29k.h
--- a29k.h 2000/03/29 13:10:42 1.14
+++ a29k.h 2000/06/26 03:41:17
@@ -98,25 +98,25 @@ extern int target_flags;
#define TARGET_MULTM ((target_flags & 1024) == 0)
#define TARGET_SWITCHES \
- { {"dw", 1, "Generate code assuming DW bit is set"}, \
- {"ndw", -1, "Generate code assuming DW bit is not set"}, \
- {"bw", 2, "Generate code using byte writes"}, \
- {"nbw", - (1|2), "Do not generate byte writes"}, \
- {"small", 4, "Use small memory model"}, \
- {"normal", - (4|8), "Use normal memory model"}, \
- {"large", 8, "Use large memory model"}, \
- {"29050", 16+128, "Generate 29050 code"}, \
- {"29000", -16, "Generate 29000 code"}, \
- {"kernel-registers", 32, "Use kernel global registers"}, \
- {"user-registers", -32, "Use user global registers"}, \
- {"stack-check", 64, "Emit stack checking code"}, \
- {"no-stack-check", - 74, "Do not emit stack checking code"}, \
- {"storem-bug", -128, "Work around storem hardware bug"}, \
- {"no-storem-bug", 128, "Do not work around storem hardware bug"}, \
- {"reuse-arg-regs", -256, "Store locals in argument registers"}, \
- {"no-reuse-arg-regs", 256, "Do not store locals in arg registers"}, \
- {"soft-float", 512, "Use software floating point"}, \
- {"no-multm", 1024, "Do not generate multm instructions"}, \
+ { {"dw", 1, N_("Generate code assuming DW bit is set")}, \
+ {"ndw", -1, N_("Generate code assuming DW bit is not set")}, \
+ {"bw", 2, N_("Generate code using byte writes")}, \
+ {"nbw", - (1|2), N_("Do not generate byte writes")}, \
+ {"small", 4, N_("Use small memory model")}, \
+ {"normal", - (4|8), N_("Use normal memory model")}, \
+ {"large", 8, N_("Use large memory model")}, \
+ {"29050", 16+128, N_("Generate 29050 code")}, \
+ {"29000", -16, N_("Generate 29000 code")}, \
+ {"kernel-registers", 32, N_("Use kernel global registers")}, \
+ {"user-registers", -32, N_("Use user global registers")}, \
+ {"stack-check", 64, N_("Emit stack checking code")}, \
+ {"no-stack-check", - 74, N_("Do not emit stack checking code")}, \
+ {"storem-bug", -128, N_("Work around storem hardware bug")}, \
+ {"no-storem-bug", 128, N_("Do not work around storem hardware bug")}, \
+ {"reuse-arg-regs", -256, N_("Store locals in argument registers")}, \
+ {"no-reuse-arg-regs", 256, N_("Do not store locals in arg registers")}, \
+ {"soft-float", 512, N_("Use software floating point")}, \
+ {"no-multm", 1024, N_("Do not generate multm instructions")}, \
{"", TARGET_DEFAULT, NULL}}
#define TARGET_DEFAULT 3
Index: config/alpha/alpha.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/alpha/alpha.h,v
retrieving revision 1.102
diff -u -p -r1.102 alpha.h
--- alpha.h 2000/06/13 21:47:40 1.102
+++ alpha.h 2000/06/26 03:41:21
@@ -196,29 +196,32 @@ extern enum alpha_fp_trap_mode alpha_fpt
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"no-soft-float", MASK_FP, "Use hardware fp"}, \
- {"soft-float", - MASK_FP, "Do not use hardware fp"}, \
- {"fp-regs", MASK_FPREGS, "Use fp registers"}, \
- {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"}, \
- {"alpha-as", -MASK_GAS, "Do not assume GAS"}, \
- {"gas", MASK_GAS, "Assume GAS"}, \
+ { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
+ {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
+ {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
+ {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
+ N_("Do not use fp registers")}, \
+ {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
+ {"gas", MASK_GAS, N_("Assume GAS")}, \
{"ieee-conformant", MASK_IEEE_CONFORMANT, \
- "Request IEEE-conformant math library routines (OSF/1)"}, \
+ N_("Request IEEE-conformant math library routines (OSF/1)")}, \
{"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
- "Emit IEEE-conformant code, without inexact exceptions"}, \
+ N_("Emit IEEE-conformant code, without inexact exceptions")}, \
{"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
- "Emit IEEE-conformant code, with inexact exceptions"}, \
+ N_("Emit IEEE-conformant code, with inexact exceptions")}, \
{"build-constants", MASK_BUILD_CONSTANTS, \
- "Do not emit complex integer constants to read-only memory"}, \
- {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"}, \
- {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
- {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
+ N_("Do not emit complex integer constants to read-only memory")}, \
+ {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
+ {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
+ {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
{"no-bwx", -MASK_BWX, ""}, \
- {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
+ {"max", MASK_MAX, \
+ N_("Emit code for the motion video ISA extension")}, \
{"no-max", -MASK_MAX, ""}, \
- {"fix", MASK_FIX, "Emit code for the fp move and sqrt ISA extension"}, \
+ {"fix", MASK_FIX, \
+ N_("Emit code for the fp move and sqrt ISA extension")}, \
{"no-fix", -MASK_FIX, ""}, \
- {"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
+ {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
{"no-cix", -MASK_CIX, ""}, \
{"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
@@ -254,15 +257,15 @@ extern const char *alpha_mlat_string; /*
#define TARGET_OPTIONS \
{ \
{"cpu=", &alpha_cpu_string, \
- "Generate code for a given CPU"}, \
+ N_("Generate code for a given CPU")}, \
{"fp-rounding-mode=", &alpha_fprm_string, \
- "Control the generated fp rounding mode"}, \
+ N_("Control the generated fp rounding mode")}, \
{"fp-trap-mode=", &alpha_fptm_string, \
- "Control the IEEE trap mode"}, \
+ N_("Control the IEEE trap mode")}, \
{"trap-precision=", &alpha_tp_string, \
- "Control the precision given to fp exceptions"}, \
+ N_("Control the precision given to fp exceptions")}, \
{"memory-latency=", &alpha_mlat_string, \
- "Tune expected memory latency"}, \
+ N_("Tune expected memory latency")}, \
}
/* Attempt to describe CPU characteristics to the preprocessor. */
Index: config/arm/arm.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.h,v
retrieving revision 1.76
diff -u -p -r1.76 arm.h
--- arm.h 2000/06/25 16:21:08 1.76
+++ arm.h 2000/06/26 03:41:25
@@ -387,96 +387,96 @@ Unrecognized value in TARGET_CPU_DEFAULT
#define SUBTARGET_SWITCHES
#endif
-#define TARGET_SWITCHES \
-{ \
- {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
- {"apcs-frame", ARM_FLAG_APCS_FRAME, \
- "Generate APCS conformant stack frames" }, \
- {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
- {"poke-function-name", ARM_FLAG_POKE, \
- "Store function names in object code" }, \
- {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
- {"fpe", ARM_FLAG_FPE, "" }, \
- {"apcs-32", ARM_FLAG_APCS_32, \
- "Use the 32bit version of the APCS" }, \
- {"apcs-26", -ARM_FLAG_APCS_32, \
- "Use the 26bit version of the APCS" }, \
- {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
- {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
- {"apcs-float", ARM_FLAG_APCS_FLOAT, \
- "Pass FP arguments in FP registers" }, \
- {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
- {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
- "Generate re-entrant, PIC code" }, \
- {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
- {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
- "The MMU will trap on unaligned accesses" }, \
- {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
- {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
- {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
- {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
- {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
- {"soft-float", ARM_FLAG_SOFT_FLOAT, \
- "Use library calls to perform FP operations" }, \
- {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
- "Use hardware floating point instructions" }, \
- {"big-endian", ARM_FLAG_BIG_END, \
- "Assume target CPU is configured as big endian" }, \
- {"little-endian", -ARM_FLAG_BIG_END, \
- "Assume target CPU is configured as little endian" }, \
- {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
- "Assume big endian bytes, little endian words" }, \
- {"thumb-interwork", ARM_FLAG_INTERWORK, \
- "Support calls between THUMB and ARM instructions sets" }, \
- {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
- {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
- "Generate a call to abort if a noreturn function returns"},\
- {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
- {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
- "Do not move instructions into a function's prologue" }, \
- {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
- {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
- "Do not load the PIC register in function prologues" }, \
- {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
- {"long-calls", ARM_FLAG_LONG_CALLS, \
- "Generate call insns as indirect calls, if necessary" }, \
- {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
- {"thumb", ARM_FLAG_THUMB, \
- "Compile for the Thumb not the ARM" }, \
- {"no-thumb", -ARM_FLAG_THUMB, "" }, \
- {"arm", -ARM_FLAG_THUMB, "" }, \
- {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
- "Thumb: Generate (non-leaf) stack frames even if not needed" }, \
- {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
- {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
- "Thumb: Generate (leaf) stack frames even if not needed" }, \
- {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
- {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
- "Thumb: Assume non-static functions may be called from ARM code" }, \
- {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
- "" }, \
- {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
- "Thumb: Assume function pointers may go to non-Thumb aware code" }, \
- {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
- "" }, \
- SUBTARGET_SWITCHES \
- {"", TARGET_DEFAULT, "" } \
+#define TARGET_SWITCHES \
+{ \
+ {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
+ {"apcs-frame", ARM_FLAG_APCS_FRAME, \
+ N_("Generate APCS conformant stack frames") }, \
+ {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
+ {"poke-function-name", ARM_FLAG_POKE, \
+ N_("Store function names in object code") }, \
+ {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
+ {"fpe", ARM_FLAG_FPE, "" }, \
+ {"apcs-32", ARM_FLAG_APCS_32, \
+ N_("Use the 32bit version of the APCS") }, \
+ {"apcs-26", -ARM_FLAG_APCS_32, \
+ N_("Use the 26bit version of the APCS") }, \
+ {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
+ {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
+ {"apcs-float", ARM_FLAG_APCS_FLOAT, \
+ N_("Pass FP arguments in FP registers") }, \
+ {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
+ {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
+ N_("Generate re-entrant, PIC code") }, \
+ {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
+ {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
+ N_("The MMU will trap on unaligned accesses") }, \
+ {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
+ {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
+ {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
+ {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
+ {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
+ {"soft-float", ARM_FLAG_SOFT_FLOAT, \
+ N_("Use library calls to perform FP operations") }, \
+ {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
+ N_("Use hardware floating point instructions") }, \
+ {"big-endian", ARM_FLAG_BIG_END, \
+ N_("Assume target CPU is configured as big endian") }, \
+ {"little-endian", -ARM_FLAG_BIG_END, \
+ N_("Assume target CPU is configured as little endian") }, \
+ {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
+ N_("Assume big endian bytes, little endian words") }, \
+ {"thumb-interwork", ARM_FLAG_INTERWORK, \
+ N_("Support calls between THUMB and ARM instructions sets") }, \
+ {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
+ {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
+ N_("Generate a call to abort if a noreturn function returns")}, \
+ {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
+ {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
+ N_("Do not move instructions into a function's prologue") }, \
+ {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
+ {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
+ N_("Do not load the PIC register in function prologues") }, \
+ {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
+ {"long-calls", ARM_FLAG_LONG_CALLS, \
+ N_("Generate call insns as indirect calls, if necessary") }, \
+ {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
+ {"thumb", ARM_FLAG_THUMB, \
+ N_("Compile for the Thumb not the ARM") }, \
+ {"no-thumb", -ARM_FLAG_THUMB, "" }, \
+ {"arm", -ARM_FLAG_THUMB, "" }, \
+ {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
+ N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
+ {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
+ {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
+ N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
+ {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
+ {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
+ N_("Thumb: Assume non-static functions may be called from ARM code") }, \
+ {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
+ "" }, \
+ {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
+ N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
+ {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
+ "" }, \
+ SUBTARGET_SWITCHES \
+ {"", TARGET_DEFAULT, "" } \
}
#define TARGET_OPTIONS \
{ \
{"cpu=", & arm_select[0].string, \
- "Specify the name of the target CPU" }, \
+ N_("Specify the name of the target CPU") }, \
{"arch=", & arm_select[1].string, \
- "Specify the name of the target architecture" }, \
+ N_("Specify the name of the target architecture") }, \
{"tune=", & arm_select[2].string, "" }, \
{"fpe=", & target_fp_name, "" }, \
{"fp=", & target_fp_name, \
- "Specify the version of the floating point emulator" }, \
- { "structure-size-boundary=", & structure_size_string, \
- "Specify the minimum bit alignment of structures" }, \
- { "pic-register=", & arm_pic_register_string, \
- "Specify the register to be used for PIC addressing" } \
+ N_("Specify the version of the floating point emulator") }, \
+ {"structure-size-boundary=", & structure_size_string, \
+ N_("Specify the minimum bit alignment of structures") }, \
+ {"pic-register=", & arm_pic_register_string, \
+ N_("Specify the register to be used for PIC addressing") } \
}
struct arm_cpu_select
Index: config/arm/pe.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/pe.h,v
retrieving revision 1.7
diff -u -p -r1.7 pe.h
--- pe.h 2000/04/08 14:29:52 1.7
+++ pe.h 2000/06/26 03:41:26
@@ -57,8 +57,9 @@ Boston, MA 02111-1307, USA. */
#define TARGET_NOP_FUN_DLLIMPORT (target_flags & TARGET_FLAG_NOP_FUN)
#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{ "nop-fun-dllimport", TARGET_FLAG_NOP_FUN, "Ignore dllimport attribute for functions" }, \
+#define SUBTARGET_SWITCHES \
+{ "nop-fun-dllimport", TARGET_FLAG_NOP_FUN, \
+ N_("Ignore dllimport attribute for functions") }, \
{ "no-nop-fun-dllimport", - TARGET_FLAG_NOP_FUN, "" },
#undef TARGET_DEFAULT
Index: config/arm/riscix.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/riscix.h,v
retrieving revision 1.6
diff -u -p -r1.6 riscix.h
--- riscix.h 1999/09/15 21:41:13 1.6
+++ riscix.h 2000/06/26 03:41:26
@@ -1,5 +1,6 @@
/* Definitions of target machine for GNU compiler. ARM RISCiX version.
- Copyright (C) 1993, 1994, 1995, 1997, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1993, 1994, 1995, 1997, 1999, 2000
+ Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original
work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
and Martin Simmons (@harleqn.co.uk).
@@ -80,9 +81,9 @@ Boston, MA 02111-1307, USA. */
switches cc1 complains about them. For the sake of argument lets allocate
bit 31 of target flags for such options. */
#define SUBTARGET_SWITCHES \
- {"bsd", 0x80000000, "Do symbol renaming for BSD"}, \
- {"xopen", 0x80000000, "Do symbol renaming for X/OPEN"}, \
- {"no-symrename", 0x80000000, "Don't do symbol renaming"},
+ {"bsd", 0x80000000, N_("Do symbol renaming for BSD")}, \
+ {"xopen", 0x80000000, N_("Do symbol renaming for X/OPEN")}, \
+ {"no-symrename", 0x80000000, N_("Don't do symbol renaming")},
/* Run-time Target Specification. */
Index: config/c4x/c4x.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/c4x/c4x.h,v
retrieving revision 1.52
diff -u -p -r1.52 c4x.h
--- c4x.h 2000/03/25 01:18:29 1.52
+++ c4x.h 2000/06/26 03:41:29
@@ -136,99 +136,99 @@
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
-#define TARGET_SWITCHES \
-{ { "small", SMALL_MEMORY_FLAG, \
- "Small memory model" }, \
- { "big", -SMALL_MEMORY_FLAG, \
- "Big memory model" }, \
- { "mpyi", MPYI_FLAG, \
- "Use MPYI instruction for C3x" }, \
- { "no-mpyi", -MPYI_FLAG, \
- "Do not use MPYI instruction for C3x" }, \
- { "fast-fix", FAST_FIX_FLAG, \
- "Use fast but approximate float to integer conversion" }, \
- { "no-fast-fix", -FAST_FIX_FLAG, \
- "Use slow but accurate float to integer conversion" }, \
- { "rpts", RPTS_FLAG, \
- "Enable use of RTPS instruction" }, \
- { "no-rpts", -RPTS_FLAG, \
- "Disable use of RTPS instruction" }, \
- { "rptb", RPTB_FLAG, \
- "Enable use of RTPB instruction" }, \
- { "no-rptb", -RPTB_FLAG, \
- "Disable use of RTPB instruction" }, \
- { "30", C30_FLAG, \
- "Generate code for C30 CPU"}, \
- { "31", C31_FLAG, \
- "Generate code for C31 CPU"}, \
- { "32", C32_FLAG, \
- "Generate code for C32 CPU"}, \
- { "33", C33_FLAG, \
- "Generate code for C33 CPU"}, \
- { "40", C40_FLAG, \
- "Generate code for C40 CPU"}, \
- { "44", C44_FLAG, \
- "Generate code for C44 CPU"}, \
- { "ti", TI_FLAG, \
- "Emit code compatible with TI tools"}, \
- { "no-ti", -TI_FLAG, \
- "Emit code to use GAS extensions"}, \
- { "paranoid", PARANOID_FLAG, \
- "Save DP across ISR in small memory model" }, \
- { "no-paranoid", -PARANOID_FLAG, \
- "Don't save DP across ISR in small memory model" }, \
- { "isr-dp-reload", PARANOID_FLAG, \
- "Save DP across ISR in small memory model" }, \
- { "no-isr-dp-reload", -PARANOID_FLAG, \
- "Don't save DP across ISR in small memory model" }, \
- { "memparm", MEMPARM_FLAG, \
- "Pass arguments on the stack" }, \
- { "regparm", -MEMPARM_FLAG, \
- "Pass arguments in registers" }, \
- { "devel", DEVEL_FLAG, \
- "Enable new features under development" }, \
- { "no-devel", -DEVEL_FLAG, \
- "Disable new features under development" }, \
- { "bk", BK_FLAG, \
- "Use the BK register as a general purpose register" }, \
- { "no-bk", -BK_FLAG, \
- "Do not allocate BK register" }, \
- { "db", DB_FLAG, \
- "Enable use of DB instruction" }, \
- { "no-db", -DB_FLAG, \
- "Disable use of DB instruction" }, \
- { "debug", DEBUG_FLAG, \
- "Enable debugging" }, \
- { "no-debug", -DEBUG_FLAG, \
- "Disable debugging" }, \
- { "hoist", HOIST_FLAG, \
- "Force constants into registers to improve hoisting" }, \
- { "no-hoist", -HOIST_FLAG, \
- "Don't force constants into registers" }, \
- { "force", FORCE_FLAG, \
- "Force RTL generation to emit valid 3 operand insns" }, \
- { "no-force", -FORCE_FLAG, \
- "Allow RTL generation to emit invalid 3 operand insns" }, \
- { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
- "Allow unsigned interation counts for RPTB/DB" }, \
- { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
- "Disallow unsigned iteration counts for RPTB/DB" }, \
- { "preserve-float", PRESERVE_FLOAT_FLAG, \
- "Preserve all 40 bits of FP reg across call" }, \
- { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
- "Only preserve 32 bits of FP reg across call" }, \
- { "parallel-insns", PARALLEL_INSN_FLAG, \
- "Enable parallel instructions" }, \
- { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
- "Disable parallel instructions" }, \
- { "parallel-mpy", PARALLEL_MPY_FLAG, \
- "Enable MPY||ADD and MPY||SUB instructions" }, \
- { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
- "Disable MPY||ADD and MPY||SUB instructions" }, \
- { "aliases", ALIASES_FLAG, \
- "Assume that pointers may be aliased" }, \
- { "no-aliases", -ALIASES_FLAG, \
- "Assume that pointers not aliased" }, \
+#define TARGET_SWITCHES \
+{ { "small", SMALL_MEMORY_FLAG, \
+ N_("Small memory model") }, \
+ { "big", -SMALL_MEMORY_FLAG, \
+ N_("Big memory model") }, \
+ { "mpyi", MPYI_FLAG, \
+ N_("Use MPYI instruction for C3x") }, \
+ { "no-mpyi", -MPYI_FLAG, \
+ N_("Do not use MPYI instruction for C3x") }, \
+ { "fast-fix", FAST_FIX_FLAG, \
+ N_("Use fast but approximate float to integer conversion") }, \
+ { "no-fast-fix", -FAST_FIX_FLAG, \
+ N_("Use slow but accurate float to integer conversion") }, \
+ { "rpts", RPTS_FLAG, \
+ N_("Enable use of RTPS instruction") }, \
+ { "no-rpts", -RPTS_FLAG, \
+ N_("Disable use of RTPS instruction") }, \
+ { "rptb", RPTB_FLAG, \
+ N_("Enable use of RTPB instruction") }, \
+ { "no-rptb", -RPTB_FLAG, \
+ N_("Disable use of RTPB instruction") }, \
+ { "30", C30_FLAG, \
+ N_("Generate code for C30 CPU")}, \
+ { "31", C31_FLAG, \
+ N_("Generate code for C31 CPU")}, \
+ { "32", C32_FLAG, \
+ N_("Generate code for C32 CPU")}, \
+ { "33", C33_FLAG, \
+ N_("Generate code for C33 CPU")}, \
+ { "40", C40_FLAG, \
+ N_("Generate code for C40 CPU")}, \
+ { "44", C44_FLAG, \
+ N_("Generate code for C44 CPU")}, \
+ { "ti", TI_FLAG, \
+ N_("Emit code compatible with TI tools")}, \
+ { "no-ti", -TI_FLAG, \
+ N_("Emit code to use GAS extensions")}, \
+ { "paranoid", PARANOID_FLAG, \
+ N_("Save DP across ISR in small memory model") }, \
+ { "no-paranoid", -PARANOID_FLAG, \
+ N_("Don't save DP across ISR in small memory model") }, \
+ { "isr-dp-reload", PARANOID_FLAG, \
+ N_("Save DP across ISR in small memory model") }, \
+ { "no-isr-dp-reload", -PARANOID_FLAG, \
+ N_("Don't save DP across ISR in small memory model") }, \
+ { "memparm", MEMPARM_FLAG, \
+ N_("Pass arguments on the stack") }, \
+ { "regparm", -MEMPARM_FLAG, \
+ N_("Pass arguments in registers") }, \
+ { "devel", DEVEL_FLAG, \
+ N_("Enable new features under development") }, \
+ { "no-devel", -DEVEL_FLAG, \
+ N_("Disable new features under development") }, \
+ { "bk", BK_FLAG, \
+ N_("Use the BK register as a general purpose register") }, \
+ { "no-bk", -BK_FLAG, \
+ N_("Do not allocate BK register") }, \
+ { "db", DB_FLAG, \
+ N_("Enable use of DB instruction") }, \
+ { "no-db", -DB_FLAG, \
+ N_("Disable use of DB instruction") }, \
+ { "debug", DEBUG_FLAG, \
+ N_("Enable debugging") }, \
+ { "no-debug", -DEBUG_FLAG, \
+ N_("Disable debugging") }, \
+ { "hoist", HOIST_FLAG, \
+ N_("Force constants into registers to improve hoisting") }, \
+ { "no-hoist", -HOIST_FLAG, \
+ N_("Don't force constants into registers") }, \
+ { "force", FORCE_FLAG, \
+ N_("Force RTL generation to emit valid 3 operand insns") }, \
+ { "no-force", -FORCE_FLAG, \
+ N_("Allow RTL generation to emit invalid 3 operand insns") }, \
+ { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
+ N_("Allow unsigned interation counts for RPTB/DB") }, \
+ { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
+ N_("Disallow unsigned iteration counts for RPTB/DB") }, \
+ { "preserve-float", PRESERVE_FLOAT_FLAG, \
+ N_("Preserve all 40 bits of FP reg across call") }, \
+ { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
+ N_("Only preserve 32 bits of FP reg across call") }, \
+ { "parallel-insns", PARALLEL_INSN_FLAG, \
+ N_("Enable parallel instructions") }, \
+ { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
+ N_("Disable parallel instructions") }, \
+ { "parallel-mpy", PARALLEL_MPY_FLAG, \
+ N_("Enable MPY||ADD and MPY||SUB instructions") }, \
+ { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
+ N_("Disable MPY||ADD and MPY||SUB instructions") }, \
+ { "aliases", ALIASES_FLAG, \
+ N_("Assume that pointers may be aliased") }, \
+ { "no-aliases", -ALIASES_FLAG, \
+ N_("Assume that pointers not aliased") }, \
{ "", TARGET_DEFAULT, ""} }
/* Default target switches. */
@@ -312,11 +312,11 @@ extern int target_flags;
extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
-#define TARGET_OPTIONS \
-{ {"rpts=", &c4x_rpts_cycles_string, \
- "Specify maximum number of iterations for RPTS" }, \
- {"cpu=", &c4x_cpu_version_string, \
- "Select CPU to generate code for" } }
+#define TARGET_OPTIONS \
+{ {"rpts=", &c4x_rpts_cycles_string, \
+ N_("Specify maximum number of iterations for RPTS") }, \
+ {"cpu=", &c4x_cpu_version_string, \
+ N_("Select CPU to generate code for") } }
/* Sometimes certain combinations of command options do not make sense
on a particular target machine. You can define a macro
Index: config/clipper/clipper.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/clipper/clipper.h,v
retrieving revision 1.14
diff -u -p -r1.14 clipper.h
--- clipper.h 2000/03/29 13:10:42 1.14
+++ clipper.h 2000/06/26 03:41:31
@@ -36,9 +36,9 @@ extern int target_flags;
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
-#define TARGET_SWITCHES \
- { { "c400", 1, "Generate code for the C400" }, \
- { "c300", -1, "Generate code for the C300" }, \
+#define TARGET_SWITCHES \
+ { { "c400", 1, N_("Generate code for the C400") }, \
+ { "c300", -1, N_("Generate code for the C300") }, \
{ "", TARGET_DEFAULT, NULL} }
#define TARGET_C400 1
Index: config/convex/convex.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/convex/convex.h,v
retrieving revision 1.9
diff -u -p -r1.9 convex.h
--- convex.h 2000/04/18 22:34:10 1.9
+++ convex.h 2000/06/26 03:41:33
@@ -48,20 +48,26 @@ extern int target_flags;
#define TARGET_DEFAULT 0
#endif
-#define TARGET_SWITCHES \
- { { "c1", 001 }, \
- { "c2", 002 }, \
- { "c32", 004 }, \
- { "c34", 010 }, \
- { "c38", 020 }, \
- { "argcount", 0100 }, \
- { "argcount-nop", 0200 }, \
- { "no-argcount", -0300 }, \
- { "volatile-cache", -0400 }, \
- { "no-volatile-cache", 0400 }, \
- { "volatile-nocache", 0400 }, \
- { "long64", 01000 }, \
- { "long32", -01000 }, \
+#define TARGET_SWITCHES \
+ { { "c1", 001, N_("Generate code for c1") }, \
+ { "c2", 002, N_("Generate code for c2") }, \
+ { "c32", 004, N_("Generate code for c32") }, \
+ { "c34", 010, N_("Generate code for c34") }, \
+ { "c38", 020, N_("Generate code for c34") }, \
+ { "argcount", 0100, \
+ N_("Use standard calling sequence, with arg count word")}, \
+ { "argcount-nop", 0200, \
+ N_("Place arg count in a nop instruction (faster than push)") }, \
+ { "no-argcount", -0300, \
+ N_("Don't push arg count, depend on symbol table") }, \
+ { "volatile-cache", -0400, \
+ N_("Use data cache for volatile mem refs (default)") }, \
+ { "no-volatile-cache", 0400, \
+ N_("Don't use data cache for volatile mem refs") }, \
+ { "volatile-nocache", 0400, \
+ N_("Bypass data cache for volatile mem refs") }, \
+ { "long64", 01000, N_("Use 64-bit longs") }, \
+ { "long32", -01000, N_("Use cc- and libc-compatible 32-bit longs")},\
{ "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}}
/* Macros used in the machine description to test the flags. */
Index: config/elxsi/elxsi.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/elxsi/elxsi.h,v
retrieving revision 1.11
diff -u -p -r1.11 elxsi.h
--- elxsi.h 2000/05/01 17:21:40 1.11
+++ elxsi.h 2000/06/26 03:41:34
@@ -47,8 +47,8 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"unix", 1, "Generate code the unix assembler can handle"}, \
- {"embos", -1, "Generate code an embedded assembler can handle"}, \
+ { {"unix", 1, N_("Generate code the unix assembler can handle")}, \
+ {"embos", -1, N_("Generate code an embedded assembler can handle")},\
{ "", TARGET_DEFAULT, NULL}}
/* Default target_flags if no switches specified. */
Index: config/fr30/fr30.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/fr30/fr30.h,v
retrieving revision 1.9
diff -u -p -r1.9 fr30.h
--- fr30.h 2000/05/12 20:57:57 1.9
+++ fr30.h 2000/06/26 03:41:37
@@ -79,12 +79,13 @@ Boston, MA 02111-1307, USA. */
/* This declaration should be present. */
extern int target_flags;
-#define TARGET_SWITCHES \
-{ \
- { "small-model", TARGET_SMALL_MODEL_MASK, "Assume small address space" }, \
- { "no-small-model", - TARGET_SMALL_MODEL_MASK, "" }, \
- { "no-lsim", 0, "" }, \
- { "", TARGET_DEFAULT, "" } \
+#define TARGET_SWITCHES \
+{ \
+ { "small-model", TARGET_SMALL_MODEL_MASK, \
+ N_("Assume small address space") }, \
+ { "no-small-model", - TARGET_SMALL_MODEL_MASK, "" }, \
+ { "no-lsim", 0, "" }, \
+ { "", TARGET_DEFAULT, "" } \
}
#define TARGET_VERSION fprintf (stderr, " (fr30)");
Index: config/fx80/fx80.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/fx80/fx80.h,v
retrieving revision 1.12
diff -u -p -r1.12 fx80.h
--- fx80.h 2000/05/22 16:22:11 1.12
+++ fx80.h 2000/06/26 03:41:39
@@ -1,5 +1,6 @@
/* Definitions of target machine for GNU compiler. Alliant FX version.
- Copyright (C) 1989, 93, 94, 95, 96, 1998, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1989, 1993, 1994, 1995, 1996, 1998, 1999, 2000
+ Free Software Foundation, Inc.
Adapted from m68k.h by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
and Joe Weening (weening@gang-of-four.stanford.edu).
@@ -109,15 +110,15 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { { "68020", 5, "Generate code for a mc68020"}, \
- { "c68020", 5, "Generate code for a mc68020"}, \
- { "bitfield", 4, "Use bitfield instructions"}, \
- { "68000", -7, "Generate code for a mc68000"}, \
- { "c68000", -7, "Generate code for a mc68000"}, \
- { "soft-float", -2, "Generate software FP code"}, \
- { "nobitfield", -4, "Do not generate bitfield insns"}, \
- { "short", 040, "Use 16bit integers"}, \
- { "noshort", -040, "Use 32bit integers"}, \
+ { { "68020", 5, N_("Generate code for a mc68020")}, \
+ { "c68020", 5, N_("Generate code for a mc68020")}, \
+ { "bitfield", 4, N_("Use bitfield instructions")}, \
+ { "68000", -7, N_("Generate code for a mc68000")}, \
+ { "c68000", -7, N_("Generate code for a mc68000")}, \
+ { "soft-float", -2, N_("Generate software FP code")}, \
+ { "nobitfield", -4, N_("Do not generate bitfield insns")}, \
+ { "short", 040, N_("Use 16bit integers")}, \
+ { "noshort", -040, N_("Use 32bit integers")}, \
{ "", TARGET_DEFAULT, NULL}}
/* target machine storage layout */
Index: config/h8300/h8300.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/h8300/h8300.h,v
retrieving revision 1.22
diff -u -p -r1.22 h8300.h
--- h8300.h 2000/05/18 16:52:10 1.22
+++ h8300.h 2000/06/26 03:41:42
@@ -99,18 +99,21 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"s", 1, "Generate H8/S code"}, \
- {"no-s", -1, "Do not generate H8/S code"}, \
- {"int32", 8, "Make integers 32 bits wide"}, \
+ { {"s", 1, N_("Generate H8/S code")}, \
+ {"no-s", -1, N_("Do not generate H8/S code")}, \
+ {"int32", 8, N_("Make integers 32 bits wide")}, \
{"addresses", 64, NULL}, \
- {"quickcall", 128, "Use registers for argument passing"}, \
- {"no-quickcall", -128, "Do not use registers for argument passing"},\
- {"slowbyte", 256, "Consider access to byte sized memory slow"},\
- {"relax", 1024, "Enable linker relaxing"}, \
+ {"quickcall", 128, \
+ N_("Use registers for argument passing")}, \
+ {"no-quickcall", -128, \
+ N_("Do not use registers for argument passing")}, \
+ {"slowbyte", 256, \
+ N_("Consider access to byte sized memory slow")}, \
+ {"relax", 1024, N_("Enable linker relaxing")}, \
{"rtl-dump", 2048, NULL}, \
- {"h", 4096, "Generate H8/300H code"}, \
- {"no-h", -4096, "Do not generate H8/300H code"}, \
- {"align-300", 8192, "Use H8/300 alignment rules"}, \
+ {"h", 4096, N_("Generate H8/300H code")}, \
+ {"no-h", -4096, N_("Do not generate H8/300H code")}, \
+ {"align-300", 8192, N_("Use H8/300 alignment rules")}, \
{ "", TARGET_DEFAULT, NULL}}
#ifdef IN_LIBGCC2
Index: config/i370/i370.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i370/i370.h,v
retrieving revision 1.22
diff -u -p -r1.22 i370.h
--- i370.h 2000/05/22 16:22:12 1.22
+++ i370.h 2000/06/26 03:41:44
@@ -60,8 +60,8 @@ extern int mvs_function_name_length;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
-{ { "char-instructions", 1, "Generate char instructions"}, \
- { "no-char-instructions", -1, "Do not generate char instructions"}, \
+{ { "char-instructions", 1, N_("Generate char instructions")}, \
+ { "no-char-instructions", -1, N_("Do not generate char instructions")}, \
{ "", TARGET_DEFAULT, 0} }
/* To use IBM supplied macro function prologue and epilogue, define the
Index: config/i386/cygwin.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/cygwin.h,v
retrieving revision 1.21
diff -u -p -r1.21 cygwin.h
--- cygwin.h 2000/05/04 18:15:07 1.21
+++ cygwin.h 2000/06/26 03:41:45
@@ -46,14 +46,18 @@ Boston, MA 02111-1307, USA. */
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
-{ "cygwin", MASK_CYGWIN, "Use the Cygwin interface" }, \
-{ "no-cygwin", MASK_WIN32, "Use the Mingw32 interface" }, \
-{ "windows", MASK_WINDOWS, "Create GUI application" }, \
-{ "console", -MASK_WINDOWS, "Create console application" }, \
-{ "dll", MASK_DLL, "Generate code for a DLL" }, \
-{ "nop-fun-dllimport", MASK_NOP_FUN_DLLIMPORT, "Ignore dllimport for functions" }, \
+{ "cygwin", MASK_CYGWIN, \
+ N_("Use the Cygwin interface") }, \
+{ "no-cygwin", MASK_WIN32, \
+ N_("Use the Mingw32 interface") }, \
+{ "windows", MASK_WINDOWS, N_("Create GUI application") }, \
+{ "console", -MASK_WINDOWS, \
+ N_("Create console application") }, \
+{ "dll", MASK_DLL, N_("Generate code for a DLL") }, \
+{ "nop-fun-dllimport", MASK_NOP_FUN_DLLIMPORT, \
+ N_("Ignore dllimport for functions") }, \
{ "no-nop-fun-dllimport", -MASK_NOP_FUN_DLLIMPORT, "" }, \
-{ "threads", 0, "Use Mingw-specific thread support" },
+{ "threads", 0, N_("Use Mingw-specific thread support") },
/* Support the __declspec keyword by turning them into attributes.
Index: config/i386/dgux.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/dgux.h,v
retrieving revision 1.9
diff -u -p -r1.9 dgux.h
--- dgux.h 2000/01/31 07:28:04 1.9
+++ dgux.h 2000/06/26 03:41:45
@@ -1,5 +1,6 @@
/* Target definitions for GNU compiler for Intel 80x86 running DG/ux
- Copyright (C) 1993, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1993, 1995, 1996, 1997, 1998, 2000
+ Free Software Foundation, Inc.
Currently maintained by gcc@dg-rtp.dg.com.
This file is part of GNU CC.
@@ -57,12 +58,17 @@ Boston, MA 02111-1307, USA. */
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
- { "standard", MASK_STANDARD, "Retain standard MXDB information" }, \
- { "legend", -MASK_NOLEGEND, "Retain legend information" }, \
- { "no-legend", MASK_NOLEGEND, "" }, \
- { "external-legend", MASK_EXTERNAL_LEGEND, "Generate external legend information" }, \
- { "identify-revision", MASK_IDENTIFY_REVISION, "Emit identifying info in .s file" }, \
- { "warn-passed-structs", MASK_WARN_PASS_STRUCT, "Warn when a function arg is a structure" },
+ { "standard", MASK_STANDARD, \
+ N_("Retain standard MXDB information") }, \
+ { "legend", -MASK_NOLEGEND, \
+ N_("Retain legend information") }, \
+ { "no-legend", MASK_NOLEGEND, "" }, \
+ { "external-legend", MASK_EXTERNAL_LEGEND, \
+ N_("Generate external legend information") }, \
+ { "identify-revision", MASK_IDENTIFY_REVISION, \
+ N_("Emit identifying info in .s file") }, \
+ { "warn-passed-structs", MASK_WARN_PASS_STRUCT, \
+ N_("Warn when a function arg is a structure") },
#undef DWARF_DEBUGGING_INFO
#define DWARF_DEBUGGING_INFO
Index: config/i386/djgpp.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/djgpp.h,v
retrieving revision 1.14
diff -u -p -r1.14 djgpp.h
--- djgpp.h 2000/05/01 16:50:49 1.14
+++ djgpp.h 2000/06/26 03:41:46
@@ -137,7 +137,7 @@ ctor_section () \
{ \
if (in_section != in_ctor) \
{ \
- fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
+ fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
in_section = in_ctor; \
} \
}
@@ -148,7 +148,7 @@ dtor_section () \
{ \
if (in_section != in_dtor) \
{ \
- fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
+ fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
in_section = in_dtor; \
} \
}
@@ -221,9 +221,11 @@ dtor_section () \
#define MASK_BNU210 (0x40000000)
#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- { "bnu210", MASK_BNU210, "Enable weak symbol and enhanced C++ template support. Binutils 2.9.5.1 or higher required." }, \
- { "no-bnu210", -MASK_BNU210, "Disable weak symbol and enhanced C++ template support." },
+#define SUBTARGET_SWITCHES \
+ { "bnu210", MASK_BNU210, \
+ N_("Enable weak symbol and enhanced C++ template support. Binutils 2.9.5.1 or higher required.") }, \
+ { "no-bnu210", -MASK_BNU210, \
+ N_("Disable weak symbol and enhanced C++ template support.") },
/* Weak symbols and .gnu.linkonce are only in the binutils snapshots
and binutils-2.10. So do it only when -mbnu210 is specified. */
Index: config/i386/i386.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.h,v
retrieving revision 1.118
diff -u -p -r1.118 i386.h
--- i386.h 2000/06/16 00:59:02 1.118
+++ i386.h 2000/06/26 03:41:49
@@ -219,67 +219,67 @@ extern const int x86_partial_reg_depende
#define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
#define TARGET_SWITCHES \
-{ { "80387", MASK_80387, "Use hardware fp" }, \
- { "no-80387", -MASK_80387, "Do not use hardware fp" }, \
- { "hard-float", MASK_80387, "Use hardware fp" }, \
- { "soft-float", -MASK_80387, "Do not use hardware fp" }, \
- { "no-soft-float", MASK_80387, "Use hardware fp" }, \
- { "386", 0, "Same as -mcpu=i386" }, \
- { "486", 0, "Same as -mcpu=i486" }, \
- { "pentium", 0, "Same as -mcpu=pentium" }, \
- { "pentiumpro", 0, "Same as -mcpu=pentiumpro" }, \
- { "rtd", MASK_RTD, "Alternate calling convention" }, \
- { "no-rtd", -MASK_RTD, "Use normal calling convention" }, \
+{ { "80387", MASK_80387, N_("Use hardware fp") }, \
+ { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
+ { "hard-float", MASK_80387, N_("Use hardware fp") }, \
+ { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
+ { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
+ { "386", 0, N_("Same as -mcpu=i386") }, \
+ { "486", 0, N_("Same as -mcpu=i486") }, \
+ { "pentium", 0, N_("Same as -mcpu=pentium") }, \
+ { "pentiumpro", 0, N_("Same as -mcpu=pentiumpro") }, \
+ { "rtd", MASK_RTD, N_("Alternate calling convention") }, \
+ { "no-rtd", -MASK_RTD, N_("Use normal calling convention") }, \
{ "align-double", MASK_ALIGN_DOUBLE, \
- "Align some doubles on dword boundary" }, \
+ N_("Align some doubles on dword boundary") }, \
{ "no-align-double", -MASK_ALIGN_DOUBLE, \
- "Align doubles on word boundary" }, \
+ N_("Align doubles on word boundary") }, \
{ "svr3-shlib", MASK_SVR3_SHLIB, \
- "Uninitialized locals in .bss" }, \
+ N_("Uninitialized locals in .bss") }, \
{ "no-svr3-shlib", -MASK_SVR3_SHLIB, \
- "Uninitialized locals in .data" }, \
+ N_("Uninitialized locals in .data") }, \
{ "ieee-fp", MASK_IEEE_FP, \
- "Use IEEE math for fp comparisons" }, \
+ N_("Use IEEE math for fp comparisons") }, \
{ "no-ieee-fp", -MASK_IEEE_FP, \
- "Do not use IEEE math for fp comparisons" }, \
+ N_("Do not use IEEE math for fp comparisons") }, \
{ "fp-ret-in-387", MASK_FLOAT_RETURNS, \
- "Return values of functions in FPU registers" }, \
+ N_("Return values of functions in FPU registers") }, \
{ "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
- "Do not return values of functions in FPU registers"}, \
+ N_("Do not return values of functions in FPU registers")}, \
{ "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
- "Do not generate sin, cos, sqrt for FPU" }, \
+ N_("Do not generate sin, cos, sqrt for FPU") }, \
{ "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
- "Generate sin, cos, sqrt for FPU"}, \
+ N_("Generate sin, cos, sqrt for FPU")}, \
{ "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
- "Omit the frame pointer in leaf functions" }, \
+ N_("Omit the frame pointer in leaf functions") }, \
{ "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
{ "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
{ "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
{ "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \
{ "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \
- { "stack-arg-probe", MASK_STACK_PROBE, "Enable stack probing" }, \
+ { "stack-arg-probe", MASK_STACK_PROBE, N_("Enable stack probing") }, \
{ "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
{ "windows", 0, 0 /* undocumented */ }, \
{ "dll", 0, 0 /* undocumented */ }, \
{ "intel-syntax", MASK_INTEL_SYNTAX, \
- "Emit Intel syntax assembler opcodes" }, \
+ N_("Emit Intel syntax assembler opcodes") }, \
{ "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
{ "align-stringops", -MASK_NO_ALIGN_STROPS, \
- "Align destination of the string operations" }, \
+ N_("Align destination of the string operations") }, \
{ "no-align-stringops", MASK_NO_ALIGN_STROPS, \
- "Do not align destination of the string operations" }, \
+ N_("Do not align destination of the string operations") }, \
{ "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
- "Inline all known string operations" }, \
+ N_("Inline all known string operations") }, \
{ "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
- "Do not inline all known string operations" }, \
+ N_("Do not inline all known string operations") }, \
{ "push-args", -MASK_NO_PUSH_ARGS, \
- "Use push instructions to save outgoing arguments" }, \
+ N_("Use push instructions to save outgoing arguments") }, \
{ "no-push-args", MASK_NO_PUSH_ARGS, \
- "Do not use push instructions to save outgoing arguments" }, \
+ N_("Do not use push instructions to save outgoing arguments") }, \
{ "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
- "Use push instructions to save outgoing arguments" }, \
+ N_("Use push instructions to save outgoing arguments") }, \
{ "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
- "Do not use push instructions to save outgoing arguments" }, \
+ N_("Do not use push instructions to save outgoing arguments") }, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT, 0 }}
@@ -312,24 +312,24 @@ extern int ix86_arch;
by appending `-m' to the specified name. */
#define TARGET_OPTIONS \
{ { "cpu=", &ix86_cpu_string, \
- "Schedule code for given CPU"}, \
+ N_("Schedule code for given CPU")}, \
{ "arch=", &ix86_arch_string, \
- "Generate code for given CPU"}, \
+ N_("Generate code for given CPU")}, \
{ "reg-alloc=", &ix86_reg_alloc_order, \
- "Control allocation order of integer registers" }, \
+ N_("Control allocation order of integer registers") }, \
{ "regparm=", &ix86_regparm_string, \
- "Number of registers used to pass integer arguments" }, \
+ N_("Number of registers used to pass integer arguments") }, \
{ "align-loops=", &ix86_align_loops_string, \
- "Loop code aligned to this power of 2" }, \
+ N_("Loop code aligned to this power of 2") }, \
{ "align-jumps=", &ix86_align_jumps_string, \
- "Jump targets are aligned to this power of 2" }, \
+ N_("Jump targets are aligned to this power of 2") }, \
{ "align-functions=", &ix86_align_funcs_string, \
- "Function starts are aligned to this power of 2" }, \
+ N_("Function starts are aligned to this power of 2") }, \
{ "preferred-stack-boundary=", \
&ix86_preferred_stack_boundary_string, \
- "Attempt to keep stack aligned to this power of 2" }, \
+ N_("Attempt to keep stack aligned to this power of 2") }, \
{ "branch-cost=", &ix86_branch_cost_string, \
- "Branches are this expensive (1-5, arbitrary units)" }, \
+ N_("Branches are this expensive (1-5, arbitrary units)") }, \
SUBTARGET_OPTIONS \
}
Index: config/i386/osf1elf.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/osf1elf.h,v
retrieving revision 1.6
diff -u -p -r1.6 osf1elf.h
--- osf1elf.h 2000/02/06 06:57:21 1.6
+++ osf1elf.h 2000/06/26 03:41:50
@@ -1,5 +1,6 @@
/* OSF/1 1.3 now is compitable with SVR4, so include sysv4.h, and
- put difference here. */
+ put difference here.
+ Copyright (C) 2000 Free Software Foundation, Inc. */
#include <stdio.h>
#include "i386/sysv4.h" /* Base i386 target machine definitions */
@@ -121,7 +122,8 @@
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
- { "mcount", -MASK_NO_MCOUNT, "Profiling uses mcount" }, \
+ { "mcount", -MASK_NO_MCOUNT, \
+ N_("Profiling uses mcount") }, \
{ "no-mcount", MASK_NO_MCOUNT, "" },
/* This macro generates the assembly code for function entry.
Index: config/i386/osfrose.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/osfrose.h,v
retrieving revision 1.12
diff -u -p -r1.12 osfrose.h
--- osfrose.h 2000/03/07 20:39:08 1.12
+++ osfrose.h 2000/06/26 03:41:51
@@ -1,6 +1,7 @@
/* Definitions of target machine for GNU compiler.
Intel 386 (OSF/1 with OSF/rose) version.
- Copyright (C) 1991, 92, 93, 96, 98, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1991, 1992, 1993, 1996, 1998, 1999, 2000
+ Free Software Foundation, Inc.
This file is part of GNU CC.
@@ -58,18 +59,27 @@ Boston, MA 02111-1307, USA. */
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
- { "half-pic", MASK_HALF_PIC, "Emit half-PIC code" }, \
+ { "half-pic", MASK_HALF_PIC, \
+ N_("Emit half-PIC code") }, \
{ "no-half-pic", -MASK_HALF_PIC, "" } \
- { "debug-half-pic", MASK_HALF_PIC_DEBUG, 0 /* intentionally undoc */ }, \
- { "debugb", MASK_HALF_PIC_DEBUG, 0 /* intentionally undoc */ }, \
- { "elf", MASK_ELF, "Emit ELF object code" }, \
- { "rose", -MASK_ELF, "Emit ROSE object code" }, \
- { "underscores", -MASK_NO_UNDERSCORES, "Symbols have a leading underscore" }, \
- { "no-underscores", MASK_NO_UNDERSCORES, "" }, \
- { "large-align", MASK_LARGE_ALIGN, "Align to >word boundaries" }, \
- { "no-large-align", -MASK_LARGE_ALIGN, "" }, \
- { "mcount", -MASK_NO_MCOUNT, "Use mcount for profiling" }, \
- { "mcount-ptr", MASK_NO_MCOUNT, "Use mcount_ptr for profiling" }, \
+ { "debug-half-pic", MASK_HALF_PIC_DEBUG, \
+ 0 /* intentionally undoc */ }, \
+ { "debugb", MASK_HALF_PIC_DEBUG, \
+ 0 /* intentionally undoc */ }, \
+ { "elf", MASK_ELF, \
+ N_("Emit ELF object code") }, \
+ { "rose", -MASK_ELF, \
+ N_("Emit ROSE object code") }, \
+ { "underscores", -MASK_NO_UNDERSCORES, \
+ N_("Symbols have a leading underscore") }, \
+ { "no-underscores", MASK_NO_UNDERSCORES, "" }, \
+ { "large-align", MASK_LARGE_ALIGN, \
+ N_("Align to >word boundaries") }, \
+ { "no-large-align", -MASK_LARGE_ALIGN, "" }, \
+ { "mcount", -MASK_NO_MCOUNT, \
+ N_("Use mcount for profiling") }, \
+ { "mcount-ptr", MASK_NO_MCOUNT, \
+ N_("Use mcount_ptr for profiling") }, \
{ "no-mcount", MASK_NO_MCOUNT, "" },
/* OSF/rose uses stabs, not dwarf. */
Index: config/i386/sco5.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/sco5.h,v
retrieving revision 1.36
diff -u -p -r1.36 sco5.h
--- sco5.h 2000/03/07 20:39:08 1.36
+++ sco5.h 2000/06/26 03:41:52
@@ -1,5 +1,5 @@
/* Definitions for Intel 386 running SCO Unix System V 3.2 Version 5.
- Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999
+ Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000
Free Software Foundation, Inc.
Contributed by Kean Johnston (hug@netcom.com)
@@ -894,9 +894,9 @@ dtors_section () \
#define TARGET_ELF (!(target_flags & MASK_COFF))
#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- { "coff", MASK_COFF, "Generate COFF output" }, \
- { "elf", -MASK_COFF, "Generate ELF output" },
+#define SUBTARGET_SWITCHES \
+ { "coff", MASK_COFF, N_("Generate COFF output") }, \
+ { "elf", -MASK_COFF, N_("Generate ELF output") },
#define NO_DOLLAR_IN_LABEL
Index: config/i386/win32.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/win32.h,v
retrieving revision 1.10
diff -u -p -r1.10 win32.h
--- win32.h 2000/02/26 21:44:42 1.10
+++ win32.h 2000/06/26 03:41:52
@@ -2,7 +2,8 @@
hosting on Windows NT 3.x, using a Unix style C library and tools,
as distinct from winnt.h, which is used to build GCC for use with a
windows style library and tool set and uses the Microsoft tools.
- Copyright (C) 1995, 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000
+ Free Software Foundation, Inc.
This file is part of GNU CC.
@@ -47,13 +48,18 @@ Boston, MA 02111-1307, USA. */
#define TARGET_NOP_FUN_DLLIMPORT (target_flags & MASK_NOP_FUN_DLLIMPORT)
#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
- { "win32", MASK_WIN32, "Use Mingw32 interface" }, \
- { "cygwin", MASK_CYGWIN, "Use Cygwin interface" }, \
- { "windows", MASK_WINDOWS, "Use bare Windows interface" }, \
- { "dll", MASK_DLL, "Generate code for a DLL" }, \
- { "nop-fun-dllimport", MASK_NOP_FUN_DLLIMPORT, "Ignore dllimport for functions" }, \
- { "no-nop-fun-dllimport", MASK_NOP_FUN_DLLIMPORT, "" },
+#define SUBTARGET_SWITCHES \
+ { "win32", MASK_WIN32, \
+ N_("Use Mingw32 interface") }, \
+ { "cygwin", MASK_CYGWIN, \
+ N_("Use Cygwin interface") }, \
+ { "windows", MASK_WINDOWS, \
+ N_("Use bare Windows interface") }, \
+ { "dll", MASK_DLL, \
+ N_("Generate code for a DLL") }, \
+ { "nop-fun-dllimport", MASK_NOP_FUN_DLLIMPORT, \
+ N_("Ignore dllimport for functions") }, \
+ { "no-nop-fun-dllimport", MASK_NOP_FUN_DLLIMPORT, "" },
#undef CPP_PREDEFINES
Index: config/i860/i860.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i860/i860.h,v
retrieving revision 1.13
diff -u -p -r1.13 i860.h
--- i860.h 2000/02/26 21:23:19 1.13
+++ i860.h 2000/06/26 03:41:54
@@ -53,9 +53,9 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"xp", 1, "Generate code which uses the FPU"}, \
- {"noxp", -1, "Do not generate code which uses the FPU"}, \
- {"xr", -1, "Do not generate code which uses the FPU"}, \
+ { {"xp", 1, N_("Generate code which uses the FPU")}, \
+ {"noxp", -1, N_("Do not generate code which uses the FPU")}, \
+ {"xr", -1, N_("Do not generate code which uses the FPU")}, \
{ "", TARGET_DEFAULT, NULL}}
#define TARGET_DEFAULT 0
Index: config/i860/paragon.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i860/paragon.h,v
retrieving revision 1.7
diff -u -p -r1.7 paragon.h
--- paragon.h 2000/03/07 20:39:08 1.7
+++ paragon.h 2000/06/26 03:41:55
@@ -1,5 +1,5 @@
/* Target definitions for GNU compiler for Intel 80860 running OSF/1AD
- Copyright (C) 1991, 1996, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1991, 1996, 1999, 2000 Free Software Foundation, Inc.
Based upon original work of Ron Guilmette (rfg@monkeys.com).
Contributed by Andy Pfiffer (andyp@ssd.intel.com).
Partially inspired by
@@ -25,10 +25,10 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_SWITCHES
#define TARGET_SWITCHES \
- { {"xp", 1, "Generate code which uses the FPU"}, \
- {"noxp", -1, "Do not generate code which uses the FPU"}, \
- {"xr", -1, "Do not generate code which uses the FPU"}, \
- {"noieee", -1, "Do not generate code which uses the FPU"}, \
+ { {"xp", 1, N_("Generate code which uses the FPU")}, \
+ {"noxp", -1, N_("Do not generate code which uses the FPU")}, \
+ {"xr", -1, N_("Do not generate code which uses the FPU")}, \
+ {"noieee", -1, N_("Do not generate code which uses the FPU")}, \
{"nx", 2, NULL}, \
{ "", TARGET_DEFAULT, NULL}}
Index: config/i960/i960.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i960/i960.h,v
retrieving revision 1.34
diff -u -p -r1.34 i960.h
--- i960.h 2000/06/01 16:29:09 1.34
+++ i960.h 2000/06/26 03:41:57
@@ -235,94 +235,94 @@ extern int target_flags;
#define TARGET_SWITCHES \
{ {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
- "Generate SA code"}, \
+ N_("Generate SA code")}, \
{"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
TARGET_FLAG_COMPLEX_ADDR), \
- "Generate SB code"}, \
+ N_("Generate SB code")}, \
/* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
- "Generate SC code"}, */ \
+ N_("Generate SC code")}, */ \
{"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
- "Generate KA code"}, \
+ N_("Generate KA code")}, \
{"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
TARGET_FLAG_COMPLEX_ADDR), \
- "Generate KB code"}, \
+ N_("Generate KB code")}, \
/* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
- "Generate KC code"}, */ \
+ N_("Generate KC code")}, */ \
{"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
- "Generate JA code"}, \
+ N_("Generate JA code")}, \
{"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
- "Generate JD code"}, \
+ N_("Generate JD code")}, \
{"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
TARGET_FLAG_COMPLEX_ADDR), \
- "Generate JF code"}, \
+ N_("Generate JF code")}, \
{"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
- "generate RP code"}, \
+ N_("generate RP code")}, \
{"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
- "Generate MC code"}, \
+ N_("Generate MC code")}, \
{"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
- "Generate CA code"}, \
+ N_("Generate CA code")}, \
/* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES| \
TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN),\
- "Generate CB code"}, \
+ N_("Generate CB code")}, \
{"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
TARGET_FLAG_CODE_ALIGN), \
- "Generate CC code"}, */ \
+ N_("Generate CC code")}, */ \
{"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
- "Generate CF code"}, \
+ N_("Generate CF code")}, \
{"numerics", (TARGET_FLAG_NUMERICS), \
- "Use hardware floating point instructions"}, \
+ N_("Use hardware floating point instructions")}, \
{"soft-float", -(TARGET_FLAG_NUMERICS), \
- "Use software floating point"}, \
+ N_("Use software floating point")}, \
{"leaf-procedures", TARGET_FLAG_LEAFPROC, \
- "Use alternate leaf function entries"}, \
+ N_("Use alternate leaf function entries")}, \
{"no-leaf-procedures", -(TARGET_FLAG_LEAFPROC), \
- "Do not use alternate leaf function entries"}, \
+ N_("Do not use alternate leaf function entries")}, \
{"tail-call", TARGET_FLAG_TAILCALL, \
- "Perform tail call optimization"}, \
+ N_("Perform tail call optimization")}, \
{"no-tail-call", -(TARGET_FLAG_TAILCALL), \
- "Do not perform tail call optimization"}, \
+ N_("Do not perform tail call optimization")}, \
{"complex-addr", TARGET_FLAG_COMPLEX_ADDR, \
- "Use complex addressing modes"}, \
+ N_("Use complex addressing modes")}, \
{"no-complex-addr", -(TARGET_FLAG_COMPLEX_ADDR), \
- "Do not use complex addressing modes"}, \
+ N_("Do not use complex addressing modes")}, \
{"code-align", TARGET_FLAG_CODE_ALIGN, \
- "Align code to 8 byte boundary"}, \
+ N_("Align code to 8 byte boundary")}, \
{"no-code-align", -(TARGET_FLAG_CODE_ALIGN), \
- "Do not align code to 8 byte boundary"}, \
+ N_("Do not align code to 8 byte boundary")}, \
/* {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE), \
- "Force use of prototypes"}, \
+ N_("Force use of prototypes")}, \
{"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE), \
- "Do not force use of prototypes"}, */ \
+ N_("Do not force use of prototypes")}, */ \
{"ic-compat", TARGET_FLAG_IC_COMPAT2_0, \
- "Enable compatibility with iC960 v2.0"}, \
+ N_("Enable compatibility with iC960 v2.0")}, \
{"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0, \
- "Enable compatibility with iC960 v2.0"}, \
+ N_("Enable compatibility with iC960 v2.0")}, \
{"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0, \
- "Enable compatibility with iC960 v3.0"}, \
+ N_("Enable compatibility with iC960 v3.0")}, \
{"asm-compat", TARGET_FLAG_ASM_COMPAT, \
- "Enable compatibility with ic960 assembler"}, \
+ N_("Enable compatibility with ic960 assembler")}, \
{"intel-asm", TARGET_FLAG_ASM_COMPAT, \
- "Enable compatibility with ic960 assembler"}, \
+ N_("Enable compatibility with ic960 assembler")}, \
{"strict-align", TARGET_FLAG_STRICT_ALIGN, \
- "Do not permit unaligned accesses"}, \
+ N_("Do not permit unaligned accesses")}, \
{"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN), \
- "Permit unaligned accesses"}, \
+ N_("Permit unaligned accesses")}, \
{"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
- "Layout types like Intel's v1.3 gcc"}, \
+ N_("Layout types like Intel's v1.3 gcc")}, \
{"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
- "Do not layout types like Intel's v1.3 gcc"}, \
+ N_("Do not layout types like Intel's v1.3 gcc")}, \
{"long-double-64", TARGET_FLAG_LONG_DOUBLE_64, \
- "Use 64 bit long doubles"}, \
+ N_("Use 64 bit long doubles")}, \
{"link-relax", 0, \
- "Enable linker relaxation"}, \
+ N_("Enable linker relaxation")}, \
{"no-link-relax", 0, \
- "Do not enable linker relaxation"}, \
+ N_("Do not enable linker relaxation")}, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT, \
NULL}}
Index: config/ia64/ia64.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/ia64/ia64.h,v
retrieving revision 1.21
diff -u -p -r1.21 ia64.h
--- ia64.h 2000/06/18 18:54:43 1.21
+++ ia64.h 2000/06/26 03:42:01
@@ -101,39 +101,39 @@ extern int target_flags;
#define TARGET_SWITCHES \
{ \
{ "big-endian", MASK_BIG_ENDIAN, \
- "Generate big endian code" }, \
+ N_("Generate big endian code") }, \
{ "little-endian", -MASK_BIG_ENDIAN, \
- "Generate little endian code" }, \
+ N_("Generate little endian code") }, \
{ "gnu-as", MASK_GNU_AS, \
- "Generate code for GNU as" }, \
+ N_("Generate code for GNU as") }, \
{ "no-gnu-as", -MASK_GNU_AS, \
- "Generate code for Intel as" }, \
+ N_("Generate code for Intel as") }, \
{ "gnu-ld", MASK_GNU_LD, \
- "Generate code for GNU ld" }, \
+ N_("Generate code for GNU ld") }, \
{ "no-gnu-ld", -MASK_GNU_LD, \
- "Generate code for Intel ld" }, \
+ N_("Generate code for Intel ld") }, \
{ "no-pic", MASK_NO_PIC, \
- "Generate code without GP reg" }, \
+ N_("Generate code without GP reg") }, \
{ "volatile-asm-stop", MASK_VOL_ASM_STOP, \
- "Emit stop bits before and after volatile extended asms" }, \
+ N_("Emit stop bits before and after volatile extended asms") }, \
{ "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
- "Don't emit stop bits before and after volatile extended asms" }, \
+ N_("Don't emit stop bits before and after volatile extended asms") }, \
{ "a-step", MASK_A_STEP, \
- "Emit code for Itanium (TM) processor A step"}, \
+ N_("Emit code for Itanium (TM) processor A step")}, \
{ "register-names", MASK_REG_NAMES, \
- "Use in/loc/out register names"}, \
+ N_("Use in/loc/out register names")}, \
{ "no-sdata", MASK_NO_SDATA, \
- "Disable use of sdata/scommon/sbss"}, \
+ N_("Disable use of sdata/scommon/sbss")}, \
{ "sdata", -MASK_NO_SDATA, \
- "Enable use of sdata/scommon/sbss"}, \
+ N_("Enable use of sdata/scommon/sbss")}, \
{ "constant-gp", MASK_CONST_GP, \
- "gp is constant (but save/restore gp on indirect calls)" }, \
+ N_("gp is constant (but save/restore gp on indirect calls)") }, \
{ "auto-pic", MASK_AUTO_PIC, \
- "Generate self-relocatable code" }, \
+ N_("Generate self-relocatable code") }, \
{ "dwarf2-asm", MASK_DWARF2_ASM, \
- "Enable Dwarf 2 line debug info via GNU as"}, \
+ N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
- "Disable Dwarf 2 line debug info via GNU as"}, \
+ N_("Disable Dwarf 2 line debug info via GNU as")}, \
{ "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
NULL } \
}
@@ -156,7 +156,7 @@ extern const char *ia64_fixed_range_stri
#define TARGET_OPTIONS \
{ \
{ "fixed-range=", &ia64_fixed_range_string, \
- "Specify range of registers to make fixed."}, \
+ N_("Specify range of registers to make fixed.")}, \
}
/* This macro is a C statement to print on `stderr' a string describing the
Index: config/m32r/m32r.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/m32r/m32r.h,v
retrieving revision 1.30
diff -u -p -r1.30 m32r.h
--- m32r.h 2000/03/29 13:10:43 1.30
+++ m32r.h 2000/06/26 03:42:05
@@ -182,15 +182,15 @@ extern int target_flags;
/* { "relax", TARGET_RELAX_MASK, "" }, \
{ "no-relax", -TARGET_RELAX_MASK, "" },*/ \
{ "debug", TARGET_DEBUG_MASK, \
- "Display compile time statistics" }, \
+ N_("Display compile time statistics") }, \
{ "align-loops", TARGET_ALIGN_LOOPS_MASK, \
- "Align all loops to 32 byte boundary" }, \
+ N_("Align all loops to 32 byte boundary") }, \
{ "no-align-loops", -TARGET_ALIGN_LOOPS_MASK, "" }, \
{ "issue-rate=1", TARGET_ISSUE_RATE_MASK, \
- "Only issue one instruction per cycle" }, \
+ N_("Only issue one instruction per cycle") }, \
{ "issue-rate=2", -TARGET_ISSUE_RATE_MASK, "" }, \
{ "branch-cost=1", TARGET_BRANCH_COST_MASK, \
- "Prefer branches over conditional execution" }, \
+ N_("Prefer branches over conditional execution") }, \
{ "branch-cost=2", -TARGET_BRANCH_COST_MASK, "" }, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT, "" } \
@@ -205,8 +205,10 @@ extern const char * m32r_sdata_string;
#define TARGET_OPTIONS \
{ \
- { "model=", & m32r_model_string, "Code size: small, medium or large" },\
- { "sdata=", & m32r_sdata_string, "Small data area: none, sdata, use" } \
+ { "model=", & m32r_model_string, \
+ N_("Code size: small, medium or large") }, \
+ { "sdata=", & m32r_sdata_string, \
+ N_("Small data area: none, sdata, use") } \
SUBTARGET_OPTIONS \
}
Index: config/mcore/mcore.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mcore/mcore.h,v
retrieving revision 1.2
diff -u -p -r1.2 mcore.h
--- mcore.h 2000/03/29 13:10:43 1.2
+++ mcore.h 2000/06/26 03:42:07
@@ -126,50 +126,50 @@ extern int target_flags;
#define TARGET_M340 (target_flags & M340_BIT)
-#define TARGET_SWITCHES \
-{ {"hardlit", HARDLIT_BIT, \
- "Inline constants if it can be done in 2 insns or less" }, \
- {"no-hardlit", - HARDLIT_BIT, \
- "inline constants if it only takes 1 instruction" }, \
- {"4align", - ALIGN8_BIT, \
- "Set maximum alignment to 4" }, \
- {"8align", ALIGN8_BIT, \
- "Set maximum alignment to 8" }, \
- {"div", DIV_BIT, \
- "" }, \
- {"no-div", - DIV_BIT, \
- "Do not use the divide instruction" }, \
- {"relax-immediates", RELAX_IMM_BIT, \
- "" }, \
- {"no-relax-immediates", - RELAX_IMM_BIT, \
- "Do not arbitary sized immediates in bit operations" }, \
- {"wide-bitfields", W_FIELD_BIT, \
- "Always treat bitfield as int-sized" }, \
- {"no-wide-bitfields", - W_FIELD_BIT, \
- "" }, \
- {"4byte-functions", OVERALIGN_FUNC_BIT, \
- "Force functions to be aligned to a 4 byte boundary" }, \
- {"no-4byte-functions", - OVERALIGN_FUNC_BIT, \
- "Force functions to be aligned to a 2 byte boundary" }, \
- {"callgraph-data", CGDATA_BIT, \
- "Emit call graph information" }, \
- {"no-callgraph-data", - CGDATA_BIT, \
- "" }, \
- {"slow-bytes", SLOW_BYTES_BIT, \
- "Prefer word accesses over byte accesses" }, \
- {"no-slow-bytes", - SLOW_BYTES_BIT, \
- "" }, \
- { "no-lsim", 0, "" }, \
- {"little-endian", LITTLE_END_BIT, \
- "Generate little endian code" }, \
- {"big-endian", - LITTLE_END_BIT, \
- "" }, \
- {"210", - M340_BIT, \
- "" }, \
- {"340", M340_BIT, \
- "Generate code for the M*Core M340" }, \
- {"", TARGET_DEFAULT, \
- "" } \
+#define TARGET_SWITCHES \
+{ {"hardlit", HARDLIT_BIT, \
+ N_("Inline constants if it can be done in 2 insns or less") }, \
+ {"no-hardlit", - HARDLIT_BIT, \
+ N_("inline constants if it only takes 1 instruction") }, \
+ {"4align", - ALIGN8_BIT, \
+ N_("Set maximum alignment to 4") }, \
+ {"8align", ALIGN8_BIT, \
+ N_("Set maximum alignment to 8") }, \
+ {"div", DIV_BIT, \
+ "" }, \
+ {"no-div", - DIV_BIT, \
+ N_("Do not use the divide instruction") }, \
+ {"relax-immediates", RELAX_IMM_BIT, \
+ "" }, \
+ {"no-relax-immediates", - RELAX_IMM_BIT, \
+ N_("Do not arbitary sized immediates in bit operations") }, \
+ {"wide-bitfields", W_FIELD_BIT, \
+ N_("Always treat bitfield as int-sized") }, \
+ {"no-wide-bitfields", - W_FIELD_BIT, \
+ "" }, \
+ {"4byte-functions", OVERALIGN_FUNC_BIT, \
+ N_("Force functions to be aligned to a 4 byte boundary") }, \
+ {"no-4byte-functions", - OVERALIGN_FUNC_BIT, \
+ N_("Force functions to be aligned to a 2 byte boundary") }, \
+ {"callgraph-data", CGDATA_BIT, \
+ N_("Emit call graph information") }, \
+ {"no-callgraph-data", - CGDATA_BIT, \
+ "" }, \
+ {"slow-bytes", SLOW_BYTES_BIT, \
+ N_("Prefer word accesses over byte accesses") }, \
+ {"no-slow-bytes", - SLOW_BYTES_BIT, \
+ "" }, \
+ { "no-lsim", 0, "" }, \
+ {"little-endian", LITTLE_END_BIT, \
+ N_("Generate little endian code") }, \
+ {"big-endian", - LITTLE_END_BIT, \
+ "" }, \
+ {"210", - M340_BIT, \
+ "" }, \
+ {"340", M340_BIT, \
+ N_("Generate code for the M*Core M340") }, \
+ {"", TARGET_DEFAULT, \
+ "" } \
}
extern char * mcore_current_function_name;
@@ -177,10 +177,10 @@ extern char * mcore_current_function_nam
/* Target specific options (as opposed to the switches above). */
extern const char * mcore_stack_increment_string;
-#define TARGET_OPTIONS \
-{ \
- {"stack-increment=", & mcore_stack_increment_string, \
- "Maximum amount for a single stack increment operation"} \
+#define TARGET_OPTIONS \
+{ \
+ {"stack-increment=", & mcore_stack_increment_string, \
+ N_("Maximum amount for a single stack increment operation")} \
}
/* The MCore ABI says that bitfields are unsigned by default. */
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mips/mips.h,v
retrieving revision 1.99
diff -u -p -r1.99 mips.h
--- mips.h 2000/06/13 21:47:42 1.99
+++ mips.h 2000/06/26 03:42:14
@@ -330,109 +330,109 @@ extern void sbss_section PARAMS ((void)
#define TARGET_SWITCHES \
{ \
{"no-crt0", 0, \
- "No default crt0.o" }, \
+ N_("No default crt0.o") }, \
{"int64", MASK_INT64 | MASK_LONG64, \
- "Use 64-bit int type"}, \
+ N_("Use 64-bit int type")}, \
{"long64", MASK_LONG64, \
- "Use 64-bit long type"}, \
+ N_("Use 64-bit long type")}, \
{"long32", -(MASK_LONG64 | MASK_INT64), \
- "Use 32-bit long type"}, \
+ N_("Use 32-bit long type")}, \
{"split-addresses", MASK_SPLIT_ADDR, \
- "Optimize lui/addiu address loads"}, \
+ N_("Optimize lui/addiu address loads")}, \
{"no-split-addresses", -MASK_SPLIT_ADDR, \
- "Don't optimize lui/addiu address loads"}, \
+ N_("Don't optimize lui/addiu address loads")}, \
{"mips-as", -MASK_GAS, \
- "Use MIPS as"}, \
+ N_("Use MIPS as")}, \
{"gas", MASK_GAS, \
- "Use GNU as"}, \
+ N_("Use GNU as")}, \
{"rnames", MASK_NAME_REGS, \
- "Use symbolic register names"}, \
+ N_("Use symbolic register names")}, \
{"no-rnames", -MASK_NAME_REGS, \
- "Don't use symbolic register names"}, \
+ N_("Don't use symbolic register names")}, \
{"gpOPT", MASK_GPOPT, \
- "Use GP relative sdata/sbss sections"}, \
+ N_("Use GP relative sdata/sbss sections")}, \
{"gpopt", MASK_GPOPT, \
- "Use GP relative sdata/sbss sections"}, \
+ N_("Use GP relative sdata/sbss sections")}, \
{"no-gpOPT", -MASK_GPOPT, \
- "Don't use GP relative sdata/sbss sections"}, \
+ N_("Don't use GP relative sdata/sbss sections")}, \
{"no-gpopt", -MASK_GPOPT, \
- "Don't use GP relative sdata/sbss sections"}, \
+ N_("Don't use GP relative sdata/sbss sections")}, \
{"stats", MASK_STATS, \
- "Output compiler statistics"}, \
+ N_("Output compiler statistics")}, \
{"no-stats", -MASK_STATS, \
- "Don't output compiler statistics"}, \
+ N_("Don't output compiler statistics")}, \
{"memcpy", MASK_MEMCPY, \
- "Don't optimize block moves"}, \
+ N_("Don't optimize block moves")}, \
{"no-memcpy", -MASK_MEMCPY, \
- "Optimize block moves"}, \
+ N_("Optimize block moves")}, \
{"mips-tfile", MASK_MIPS_TFILE, \
- "Use mips-tfile asm postpass"}, \
+ N_("Use mips-tfile asm postpass")}, \
{"no-mips-tfile", -MASK_MIPS_TFILE, \
- "Don't use mips-tfile asm postpass"}, \
+ N_("Don't use mips-tfile asm postpass")}, \
{"soft-float", MASK_SOFT_FLOAT, \
- "Use software floating point"}, \
+ N_("Use software floating point")}, \
{"hard-float", -MASK_SOFT_FLOAT, \
- "Use hardware floating point"}, \
+ N_("Use hardware floating point")}, \
{"fp64", MASK_FLOAT64, \
- "Use 64-bit FP registers"}, \
+ N_("Use 64-bit FP registers")}, \
{"fp32", -MASK_FLOAT64, \
- "Use 32-bit FP registers"}, \
+ N_("Use 32-bit FP registers")}, \
{"gp64", MASK_64BIT, \
- "Use 64-bit general registers"}, \
+ N_("Use 64-bit general registers")}, \
{"gp32", -MASK_64BIT, \
- "Use 32-bit general registers"}, \
+ N_("Use 32-bit general registers")}, \
{"abicalls", MASK_ABICALLS, \
- "Use Irix PIC"}, \
+ N_("Use Irix PIC")}, \
{"no-abicalls", -MASK_ABICALLS, \
- "Don't use Irix PIC"}, \
+ N_("Don't use Irix PIC")}, \
{"half-pic", MASK_HALF_PIC, \
- "Use OSF PIC"}, \
+ N_("Use OSF PIC")}, \
{"no-half-pic", -MASK_HALF_PIC, \
- "Don't use OSF PIC"}, \
+ N_("Don't use OSF PIC")}, \
{"long-calls", MASK_LONG_CALLS, \
- "Use indirect calls"}, \
+ N_("Use indirect calls")}, \
{"no-long-calls", -MASK_LONG_CALLS, \
- "Don't use indirect calls"}, \
+ N_("Don't use indirect calls")}, \
{"embedded-pic", MASK_EMBEDDED_PIC, \
- "Use embedded PIC"}, \
+ N_("Use embedded PIC")}, \
{"no-embedded-pic", -MASK_EMBEDDED_PIC, \
- "Don't use embedded PIC"}, \
+ N_("Don't use embedded PIC")}, \
{"embedded-data", MASK_EMBEDDED_DATA, \
- "Use ROM instead of RAM"}, \
+ N_("Use ROM instead of RAM")}, \
{"no-embedded-data", -MASK_EMBEDDED_DATA, \
- "Don't use ROM instead of RAM"}, \
+ N_("Don't use ROM instead of RAM")}, \
{"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
- "Put uninitialized constants in ROM (needs -membedded-data)"}, \
+ N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
{"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
- "Don't put uninitialized constants in ROM"}, \
+ N_("Don't put uninitialized constants in ROM")}, \
{"eb", MASK_BIG_ENDIAN, \
- "Use big-endian byte order"}, \
+ N_("Use big-endian byte order")}, \
{"el", -MASK_BIG_ENDIAN, \
- "Use little-endian byte order"}, \
+ N_("Use little-endian byte order")}, \
{"single-float", MASK_SINGLE_FLOAT, \
- "Use single (32-bit) FP only"}, \
+ N_("Use single (32-bit) FP only")}, \
{"double-float", -MASK_SINGLE_FLOAT, \
- "Don't use single (32-bit) FP only"}, \
+ N_("Don't use single (32-bit) FP only")}, \
{"mad", MASK_MAD, \
- "Use multiply accumulate"}, \
+ N_("Use multiply accumulate")}, \
{"no-mad", -MASK_MAD, \
- "Don't use multiply accumulate"}, \
+ N_("Don't use multiply accumulate")}, \
{"fix4300", MASK_4300_MUL_FIX, \
- "Work around early 4300 hardware bug"}, \
+ N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
- "Don't work around early 4300 hardware bug"}, \
+ N_("Don't work around early 4300 hardware bug")}, \
{"4650", MASK_MAD | MASK_SINGLE_FLOAT, \
- "Optimize for 4650"}, \
+ N_("Optimize for 4650")}, \
{"3900", MASK_MIPS3900, \
- "Optimize for 3900"}, \
+ N_("Optimize for 3900")}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
- "Trap on integer divide by zero"}, \
+ N_("Trap on integer divide by zero")}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
- "Don't trap on integer divide by zero"}, \
+ N_("Don't trap on integer divide by zero")}, \
{"check-range-division",MASK_CHECK_RANGE_DIV, \
- "Trap on integer divide overflow"}, \
+ N_("Trap on integer divide overflow")}, \
{"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
- "Don't trap on integer divide overflow"}, \
+ N_("Don't trap on integer divide overflow")}, \
{"debug", MASK_DEBUG, \
NULL}, \
{"debuga", MASK_DEBUG_A, \
@@ -551,13 +551,13 @@ extern void sbss_section PARAMS ((void)
{ \
SUBTARGET_TARGET_OPTIONS \
{ "cpu=", &mips_cpu_string, \
- "Specify CPU for scheduling purposes"}, \
+ N_("Specify CPU for scheduling purposes")}, \
{ "ips", &mips_isa_string, \
- "Specify MIPS ISA"}, \
+ N_("Specify MIPS ISA")}, \
{ "entry", &mips_entry_string, \
- "Use mips16 entry/exit psuedo ops"}, \
+ N_("Use mips16 entry/exit psuedo ops")}, \
{ "no-mips16", &mips_no_mips16_string, \
- "Don't use MIPS16 instructions"}, \
+ N_("Don't use MIPS16 instructions")}, \
{ "explicit-type-size", &mips_explicit_type_size_string, \
NULL}, \
}
Index: config/mn10300/mn10300.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mn10300/mn10300.h,v
retrieving revision 1.35
diff -u -p -r1.35 mn10300.h
--- mn10300.h 2000/05/16 10:49:58 1.35
+++ mn10300.h 2000/06/26 03:42:15
@@ -53,11 +53,11 @@ extern int target_flags;
#define TARGET_AM33 (target_flags & 0x2)
#define TARGET_SWITCHES \
- {{ "mult-bug", 0x1, "Work around hardware multiply bug"}, \
- { "no-mult-bug", -0x1, "Do not work around hardware multiply bug"},\
- { "am33", 0x2}, \
- { "am33", -(0x1)},\
- { "no-am33", -0x2}, \
+ {{ "mult-bug", 0x1, N_("Work around hardware multiply bug")}, \
+ { "no-mult-bug", -0x1, N_("Do not work around hardware multiply bug")},\
+ { "am33", 0x2, 0}, \
+ { "am33", -(0x1), 0},\
+ { "no-am33", -0x2, 0}, \
{ "", TARGET_DEFAULT, NULL}}
#ifndef TARGET_DEFAULT
Index: config/ns32k/ns32k.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/ns32k/ns32k.h,v
retrieving revision 1.14
diff -u -p -r1.14 ns32k.h
--- ns32k.h 2000/03/23 00:29:54 1.14
+++ ns32k.h 2000/06/26 03:42:18
@@ -99,28 +99,30 @@ extern int target_flags;
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
-#define TARGET_SWITCHES \
- { { "32081", 1, "Use hardware fp"}, \
- { "soft-float", -257, "Don't use hardware fp"}, \
- { "rtd", 2, "Alternative calling convention"}, \
- { "nortd", -2, "Use normal calling convention"}, \
- { "regparm", 4, "Pass some arguments in registers"}, \
- { "noregparm", -4, "Pass all arguments on stack"}, \
- { "32532", 24, "Optimize for 32532 cpu"}, \
- { "32332", 16, "Optimize for 32332 cpu"}, \
- { "32332", -8, 0}, \
- { "32032", -24, "Optimize for 32032"}, \
- { "sb", -32, "Register sb is zero. Use for absolute addressing"}, \
- { "nosb", 32, "Do not use register sb"}, \
- { "bitfield", -64, "Do not use bitfield instructions"}, \
- { "nobitfield", 64, "Use bitfield instructions"}, \
- { "himem", 128, "Generate code for high memory"}, \
- { "nohimem", -128, "Generate code for low memory"}, \
- { "32381", 256, "32381 fpu"}, \
- { "mult-add", 512, "Use multiply-accumulate fp instructions"}, \
- { "nomult-add", -512, "Do not use multiply-accumulate fp instructions" }, \
- { "src", 1024, "\"Small register classes\" kludge"}, \
- { "nosrc", -1024, "No \"Small register classes\" kludge"}, \
+#define TARGET_SWITCHES \
+ { { "32081", 1, N_("Use hardware fp")}, \
+ { "soft-float", -257, N_("Don't use hardware fp")}, \
+ { "rtd", 2, N_("Alternative calling convention")}, \
+ { "nortd", -2, N_("Use normal calling convention")}, \
+ { "regparm", 4, N_("Pass some arguments in registers")}, \
+ { "noregparm", -4, N_("Pass all arguments on stack")}, \
+ { "32532", 24, N_("Optimize for 32532 cpu")}, \
+ { "32332", 16, N_("Optimize for 32332 cpu")}, \
+ { "32332", -8, 0}, \
+ { "32032", -24, N_("Optimize for 32032")}, \
+ { "sb", -32, \
+ N_("Register sb is zero. Use for absolute addressing")}, \
+ { "nosb", 32, N_("Do not use register sb")}, \
+ { "bitfield", -64, N_("Do not use bitfield instructions")}, \
+ { "nobitfield", 64, N_("Use bitfield instructions")}, \
+ { "himem", 128, N_("Generate code for high memory")}, \
+ { "nohimem", -128, N_("Generate code for low memory")}, \
+ { "32381", 256, N_("32381 fpu")}, \
+ { "mult-add", 512, N_("Use multiply-accumulate fp instructions")}, \
+ { "nomult-add", -512, \
+ N_("Do not use multiply-accumulate fp instructions") }, \
+ { "src", 1024, N_("\"Small register classes\" kludge")}, \
+ { "nosrc", -1024, N_("No \"Small register classes\" kludge")}, \
{ "", TARGET_DEFAULT, 0}}
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
Index: config/pdp11/pdp11.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/pdp11/pdp11.h,v
retrieving revision 1.20
diff -u -p -r1.20 pdp11.h
--- pdp11.h 2000/05/24 04:44:25 1.20
+++ pdp11.h 2000/06/26 03:42:20
@@ -51,45 +51,45 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
-{ { "fpu", 1, "Use hardware floating point" }, \
- { "soft-float", -1, "Do not use hardware floating point" }, \
-/* return float result in ac0 */ \
- { "ac0", 2, "Return floating point results in ac0" }, \
- { "no-ac0", -2, "Return floating point results in memory" },\
-/* is 11/40 */ \
- { "40", 4, "Generate code for an 11/40" }, \
- { "no-40", -4, "" }, \
-/* is 11/45 */ \
- { "45", 8, "Generate code for an 11/45" }, \
- { "no-45", -8, "" }, \
-/* is 11/10 */ \
- { "10", -12, "Generate code for an 11/10" }, \
-/* use movstrhi for bcopy */ \
- { "bcopy", 16, NULL }, \
- { "bcopy-builtin", -16, NULL }, \
-/* use 32 bit for int */ \
- { "int32", 32, "Use 32 bit int" }, \
- { "no-int16", 32, "Use 32 bit int" }, \
- { "int16", -32, "Use 16 bit int" }, \
- { "no-int32", -32, "Use 16 bit int" }, \
-/* use 32 bit for float */ \
- { "float32", 64, "Use 32 bit float" }, \
- { "no-float64", 64, "Use 32 bit float" }, \
- { "float64", -64, "Use 64 bit float" }, \
- { "no-float32", -64, "Use 64 bit float" }, \
+{ { "fpu", 1, N_("Use hardware floating point") }, \
+ { "soft-float", -1, N_("Do not use hardware floating point") }, \
+/* return float result in ac0 */ \
+ { "ac0", 2, N_("Return floating point results in ac0") }, \
+ { "no-ac0", -2, N_("Return floating point results in memory") }, \
+/* is 11/40 */ \
+ { "40", 4, N_("Generate code for an 11/40") }, \
+ { "no-40", -4, "" }, \
+/* is 11/45 */ \
+ { "45", 8, N_("Generate code for an 11/45") }, \
+ { "no-45", -8, "" }, \
+/* is 11/10 */ \
+ { "10", -12, N_("Generate code for an 11/10") }, \
+/* use movstrhi for bcopy */ \
+ { "bcopy", 16, NULL }, \
+ { "bcopy-builtin", -16, NULL }, \
+/* use 32 bit for int */ \
+ { "int32", 32, N_("Use 32 bit int") }, \
+ { "no-int16", 32, N_("Use 32 bit int") }, \
+ { "int16", -32, N_("Use 16 bit int") }, \
+ { "no-int32", -32, N_("Use 16 bit int") }, \
+/* use 32 bit for float */ \
+ { "float32", 64, N_("Use 32 bit float") }, \
+ { "no-float64", 64, N_("Use 32 bit float") }, \
+ { "float64", -64, N_("Use 64 bit float") }, \
+ { "no-float32", -64, N_("Use 64 bit float") }, \
/* allow abshi pattern? - can trigger "optimizations" which make code SLOW! */\
- { "abshi", 128, NULL }, \
- { "no-abshi", -128, NULL }, \
+ { "abshi", 128, NULL }, \
+ { "no-abshi", -128, NULL }, \
/* is branching expensive - on a PDP, it's actually really cheap */ \
/* this is just to play around and check what code gcc generates */ \
- { "branch-expensive", 256, NULL }, \
- { "branch-cheap", -256, NULL }, \
-/* split instruction and data memory? */ \
- { "split", 1024, "Target has split I&D" }, \
- { "no-split", -1024, "Target does not have split I&D" }, \
-/* UNIX assembler syntax? */ \
- { "unix-asm", 2048, "Use UNIX assembler syntax" }, \
- { "dec-asm", -2048, "Use DEC assembler syntax" }, \
+ { "branch-expensive", 256, NULL }, \
+ { "branch-cheap", -256, NULL }, \
+/* split instruction and data memory? */ \
+ { "split", 1024, N_("Target has split I&D") }, \
+ { "no-split", -1024, N_("Target does not have split I&D") }, \
+/* UNIX assembler syntax? */ \
+ { "unix-asm", 2048, N_("Use UNIX assembler syntax") }, \
+ { "dec-asm", -2048, N_("Use DEC assembler syntax") }, \
/* default */ \
{ "", TARGET_DEFAULT, NULL} \
}
Index: config/pj/pj.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/pj/pj.h,v
retrieving revision 1.2
diff -u -p -r1.2 pj.h
--- pj.h 2000/03/08 06:27:35 1.2
+++ pj.h 2000/06/26 03:42:22
@@ -69,12 +69,18 @@ extern int target_flags;
#endif
#define TARGET_SWITCHES \
-{ {"l", LITTLE_ENDIAN_BIT, "Generate little endian data" }, \
- {"b", -LITTLE_ENDIAN_BIT, "Generate big endian data" }, \
- {"t", PJ_TEST_BIT, "Turn on maintainer testing code" }, \
- {"ext", EXTENSIONS_BIT, "Enable Transmeta picoJava extensions" }, \
- {"no-ext", -EXTENSIONS_BIT, "Disable Transmeta picoJava extensions" }, \
- {"no-reorg", -REORG_BIT, "Disable reorganization pass" }, \
+{ {"l", LITTLE_ENDIAN_BIT, \
+ N_("Generate little endian data") }, \
+ {"b", -LITTLE_ENDIAN_BIT, \
+ N_("Generate big endian data") }, \
+ {"t", PJ_TEST_BIT, \
+ N_("Turn on maintainer testing code") }, \
+ {"ext", EXTENSIONS_BIT, \
+ N_("Enable Transmeta picoJava extensions") }, \
+ {"no-ext", -EXTENSIONS_BIT, \
+ N_("Disable Transmeta picoJava extensions") }, \
+ {"no-reorg", -REORG_BIT, \
+ N_("Disable reorganization pass") }, \
{"", TARGET_DEFAULT, 0 }}
/* Sometimes certain combinations of command options do not make
Index: config/rs6000/aix.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/aix.h,v
retrieving revision 1.3
diff -u -p -r1.3 aix.h
--- aix.h 2000/03/29 04:06:13 1.3
+++ aix.h 2000/06/26 03:42:23
@@ -251,9 +251,9 @@ toc_section () \
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
{"xl-call", MASK_XL_CALL, \
- "Always pass floating-point arguments in memory" }, \
+ N_("Always pass floating-point arguments in memory") }, \
{"no-xl-call", - MASK_XL_CALL, \
- "Don't always pass floating-point arguments in memory" }, \
+ N_("Don't always pass floating-point arguments in memory") }, \
SUBSUBTARGET_SWITCHES
#define SUBSUBTARGET_SWITCHES
Index: config/rs6000/aix41.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/aix41.h,v
retrieving revision 1.11
diff -u -p -r1.11 aix41.h
--- aix41.h 2000/06/12 19:58:57 1.11
+++ aix41.h 2000/06/26 03:42:23
@@ -28,7 +28,7 @@ Boston, MA 02111-1307, USA. */
#undef SUBSUBTARGET_SWITCHES
#define SUBSUBTARGET_SWITCHES \
{"pe", 0, \
- "Support message passing with the Parallel Environment" },
+ N_("Support message passing with the Parallel Environment") },
#undef ASM_SPEC
#define ASM_SPEC "-u %(asm_cpu)"
Index: config/rs6000/aix43.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/aix43.h,v
retrieving revision 1.13
diff -u -p -r1.13 aix43.h
--- aix43.h 2000/06/12 19:58:57 1.13
+++ aix43.h 2000/06/26 03:42:23
@@ -28,11 +28,11 @@ Boston, MA 02111-1307, USA. */
#undef SUBSUBTARGET_SWITCHES
#define SUBSUBTARGET_SWITCHES \
{"aix64", MASK_64BIT | MASK_POWERPC64 | MASK_POWERPC, \
- "Compile for 64-bit pointers" }, \
+ N_("Compile for 64-bit pointers") }, \
{"aix32", - (MASK_64BIT | MASK_POWERPC64), \
- "Compile for 32-bit pointers" }, \
+ N_("Compile for 32-bit pointers") }, \
{"pe", 0, \
- "Support message passing with the Parallel Environment" },
+ N_("Support message passing with the Parallel Environment") },
/* Sometimes certain combinations of command options do not make sense
on a particular target machine. You can define a macro
Index: config/rs6000/beos.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/beos.h,v
retrieving revision 1.3
diff -u -p -r1.3 beos.h
--- beos.h 2000/03/16 03:16:40 1.3
+++ beos.h 2000/06/26 03:42:23
@@ -29,9 +29,11 @@ Boston, MA 02111-1307, USA. */
#define TARGET_XL_CALL (target_flags & MASK_XL_CALL)
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
- {"xl-call", MASK_XL_CALL}, \
- {"no-xl-call", - MASK_XL_CALL}, \
- {"threads", 0}, \
+ {"xl-call", MASK_XL_CALL, \
+ N_("Always pass floating-point arguments in memory") }, \
+ {"no-xl-call", - MASK_XL_CALL, \
+ N_("Don't always pass floating-point arguments in memory") }, \
+ {"threads", 0}, \
{"pe", 0},
#undef ASM_SPEC
Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.84
diff -u -p -r1.84 rs6000.h
--- rs6000.h 2000/06/13 21:47:43 1.84
+++ rs6000.h 2000/06/26 03:42:27
@@ -253,81 +253,81 @@ extern int target_flags;
#define TARGET_SWITCHES \
{{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
- "Use POWER instruction set"}, \
+ N_("Use POWER instruction set")}, \
{"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
| MASK_POWER2), \
- "Use POWER2 instruction set"}, \
+ N_("Use POWER2 instruction set")}, \
{"no-power2", - MASK_POWER2, \
- "Do not use POWER2 instruction set"}, \
+ N_("Do not use POWER2 instruction set")}, \
{"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
| MASK_STRING), \
- "Do not use POWER instruction set"}, \
+ N_("Do not use POWER instruction set")}, \
{"powerpc", MASK_POWERPC, \
- "Use PowerPC instruction set"}, \
+ N_("Use PowerPC instruction set")}, \
{"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
| MASK_PPC_GFXOPT | MASK_POWERPC64), \
- "Do not use PowerPC instruction set"}, \
+ N_("Do not use PowerPC instruction set")}, \
{"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
- "Use PowerPC General Purpose group optional instructions"},\
+ N_("Use PowerPC General Purpose group optional instructions")},\
{"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
- "Don't use PowerPC General Purpose group optional instructions"},\
+ N_("Don't use PowerPC General Purpose group optional instructions")},\
{"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
- "Use PowerPC Graphics group optional instructions"},\
+ N_("Use PowerPC Graphics group optional instructions")},\
{"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
- "Don't use PowerPC Graphics group optional instructions"},\
+ N_("Don't use PowerPC Graphics group optional instructions")},\
{"powerpc64", MASK_POWERPC64, \
- "Use PowerPC-64 instruction set"}, \
+ N_("Use PowerPC-64 instruction set")}, \
{"no-powerpc64", - MASK_POWERPC64, \
- "Don't use PowerPC-64 instruction set"}, \
+ N_("Don't use PowerPC-64 instruction set")}, \
{"new-mnemonics", MASK_NEW_MNEMONICS, \
- "Use new mnemonics for PowerPC architecture"}, \
+ N_("Use new mnemonics for PowerPC architecture")},\
{"old-mnemonics", -MASK_NEW_MNEMONICS, \
- "Use old mnemonics for PowerPC architecture"}, \
+ N_("Use old mnemonics for PowerPC architecture")},\
{"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
| MASK_MINIMAL_TOC), \
- "Put everything in the regular TOC"}, \
+ N_("Put everything in the regular TOC")}, \
{"fp-in-toc", - MASK_NO_FP_IN_TOC, \
- "Place floating point constants in TOC"}, \
+ N_("Place floating point constants in TOC")}, \
{"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
- "Don't place floating point constants in TOC"}, \
+ N_("Don't place floating point constants in TOC")},\
{"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
- "Place symbol+offset constants in TOC"}, \
+ N_("Place symbol+offset constants in TOC")}, \
{"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
- "Don't place symbol+offset constants in TOC"}, \
+ N_("Don't place symbol+offset constants in TOC")},\
{"minimal-toc", MASK_MINIMAL_TOC, \
"Use only one TOC entry per procedure"}, \
{"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
- ""}, \
+ ""}, \
{"no-minimal-toc", - MASK_MINIMAL_TOC, \
- "Place variable addresses in the regular TOC"}, \
+ N_("Place variable addresses in the regular TOC")},\
{"hard-float", - MASK_SOFT_FLOAT, \
- "Use hardware fp"}, \
+ N_("Use hardware fp")}, \
{"soft-float", MASK_SOFT_FLOAT, \
- "Do not use hardware fp"}, \
+ N_("Do not use hardware fp")}, \
{"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
- "Generate load/store multiple instructions"}, \
+ N_("Generate load/store multiple instructions")}, \
{"no-multiple", - MASK_MULTIPLE, \
- "Do not generate load/store multiple instructions"},\
+ N_("Do not generate load/store multiple instructions")},\
{"no-multiple", MASK_MULTIPLE_SET, \
- ""},\
+ ""}, \
{"string", MASK_STRING | MASK_STRING_SET, \
- "Generate string instructions for block moves"},\
+ N_("Generate string instructions for block moves")},\
{"no-string", - MASK_STRING, \
- "Do not generate string instructions for block moves"},\
+ N_("Do not generate string instructions for block moves")},\
{"no-string", MASK_STRING_SET, \
- ""},\
+ ""}, \
{"update", - MASK_NO_UPDATE, \
- "Generate load/store with update instructions"},\
+ N_("Generate load/store with update instructions")},\
{"no-update", MASK_NO_UPDATE, \
- "Do not generate load/store with update instructions"},\
+ N_("Do not generate load/store with update instructions")},\
{"fused-madd", - MASK_NO_FUSED_MADD, \
- "Generate fused multiply/add instructions"}, \
+ N_("Generate fused multiply/add instructions")},\
{"no-fused-madd", MASK_NO_FUSED_MADD, \
- "Don't generate fused multiply/add instructions"},\
+ N_("Don't generate fused multiply/add instructions")},\
{"sched-prolog", MASK_SCHED_PROLOG, \
""}, \
{"no-sched-prolog", -MASK_SCHED_PROLOG, \
- "Don't schedule the start and end of the procedure"},\
+ N_("Don't schedule the start and end of the procedure")},\
{"sched-epilog", MASK_SCHED_PROLOG, \
""}, \
{"no-sched-epilog", -MASK_SCHED_PROLOG, \
@@ -399,9 +399,11 @@ extern enum processor_type rs6000_cpu;
#define TARGET_OPTIONS \
{ \
- {"cpu=", &rs6000_select[1].string, "Use features of and schedule code for given CPU" },\
- {"tune=", &rs6000_select[2].string, "Schedule code for given CPU" }, \
- {"debug=", &rs6000_debug_name, "Enable debug output" }, \
+ {"cpu=", &rs6000_select[1].string, \
+ N_("Use features of and schedule code for given CPU") }, \
+ {"tune=", &rs6000_select[2].string, \
+ N_("Schedule code for given CPU") }, \
+ {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
SUBTARGET_OPTIONS \
}
Index: config/rs6000/sysv4.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/sysv4.h,v
retrieving revision 1.30
diff -u -p -r1.30 sysv4.h
--- sysv4.h 2000/05/16 22:49:01 1.30
+++ sysv4.h 2000/06/26 03:42:29
@@ -87,8 +87,8 @@ extern const char *rs6000_sdata_name;
/* Override rs6000.h definition. */
#undef SUBTARGET_OPTIONS
#define SUBTARGET_OPTIONS \
- { "call-", &rs6000_abi_name, "Select ABI calling convention." }, \
- { "sdata=", &rs6000_sdata_name, "Select method for sdata handling." }
+ { "call-", &rs6000_abi_name, N_("Select ABI calling convention.") }, \
+ { "sdata=", &rs6000_sdata_name, N_("Select method for sdata handling.") }
/* Max # of bytes for variables to automatically be put into the .sdata
or .sdata2 sections. */
@@ -102,40 +102,59 @@ extern int g_switch_set; /* Whether -G
/* Override rs6000.h definition. */
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
- { "bit-align", -MASK_NO_BITFIELD_TYPE, "Align to the base type of the bitfield." },\
- { "no-bit-align", MASK_NO_BITFIELD_TYPE, "Don't align to the base type of the bitfield." },\
- { "strict-align", MASK_STRICT_ALIGN, "Don't assume that unaligned accesses are handled by the system" },\
- { "no-strict-align", -MASK_STRICT_ALIGN, "Assume that unaligned accesses are handled by the system" },\
- { "relocatable", MASK_RELOCATABLE | MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC, "Produce code relocatable at runtime." },\
- { "no-relocatable", -MASK_RELOCATABLE, "Don't produce code relocatable at runtime." },\
- { "relocatable-lib", MASK_RELOCATABLE | MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC, "Produce code relocatable at runtime." },\
- { "no-relocatable-lib", -MASK_RELOCATABLE, "Don't produce code relocatable at runtime." },\
- { "little-endian", MASK_LITTLE_ENDIAN, "Produce little endian code." }, \
- { "little", MASK_LITTLE_ENDIAN, "Produce little endian code." }, \
- { "big-endian", -MASK_LITTLE_ENDIAN, "Produce big endian code." }, \
- { "big", -MASK_LITTLE_ENDIAN, "Produce big endian code." }, \
- { "no-toc", 0, "no description yet" }, \
- { "toc", MASK_MINIMAL_TOC, "no description yet" }, \
- { "full-toc", MASK_MINIMAL_TOC, "no description yet" }, \
- { "prototype", MASK_PROTOTYPE, "no description yet" }, \
- { "no-prototype", -MASK_PROTOTYPE, "no description yet" }, \
- { "no-traceback", 0, "no description yet" }, \
- { "eabi", MASK_EABI, "Use EABI." }, \
- { "no-eabi", -MASK_EABI, "Don't use EABI." }, \
- { "regnames", MASK_REGNAMES, "Use alternate register names." }, \
- { "no-regnames", -MASK_REGNAMES, "Don't use alternate register names." },\
- { "sdata", 0, "no description yet" }, \
- { "no-sdata", 0, "no description yet" }, \
- { "sim", 0, "Link with libsim.a, libc.a and sim-crt0.o." }, \
- { "ads", 0, "Link with libads.a, libc.a and crt0.o." }, \
- { "yellowknife", 0, "Link with libyk.a, libc.a and crt0.o." }, \
- { "mvme", 0, "Link with libmvme.a, libc.a and crt0.o." }, \
- { "emb", 0, "Set the PPC_EMB bit in the ELF flags header" }, \
- { "vxworks", 0, "no description yet" }, \
- { "solaris-cclib", 0, "no description yet" }, \
- { "shlib", 0, "no description yet" }, \
- EXTRA_SUBTARGET_SWITCHES \
- { "newlib", 0, "no description yet" },
+ { "bit-align", -MASK_NO_BITFIELD_TYPE, \
+ N_("Align to the base type of the bitfield.") }, \
+ { "no-bit-align", MASK_NO_BITFIELD_TYPE, \
+ N_("Don't align to the base type of the bitfield.") }, \
+ { "strict-align", MASK_STRICT_ALIGN, \
+ N_("Don't assume that unaligned accesses are handled by the system") }, \
+ { "no-strict-align", -MASK_STRICT_ALIGN, \
+ N_("Assume that unaligned accesses are handled by the system") }, \
+ { "relocatable", MASK_RELOCATABLE | MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC, \
+ N_("Produce code relocatable at runtime.") }, \
+ { "no-relocatable", -MASK_RELOCATABLE, \
+ N_("Don't produce code relocatable at runtime.") }, \
+ { "relocatable-lib", MASK_RELOCATABLE | MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC, \
+ N_("Produce code relocatable at runtime.") }, \
+ { "no-relocatable-lib", -MASK_RELOCATABLE, \
+ N_("Don't produce code relocatable at runtime.") }, \
+ { "little-endian", MASK_LITTLE_ENDIAN, \
+ N_("Produce little endian code.") }, \
+ { "little", MASK_LITTLE_ENDIAN, \
+ N_("Produce little endian code.") }, \
+ { "big-endian", -MASK_LITTLE_ENDIAN, \
+ N_("Produce big endian code.") }, \
+ { "big", -MASK_LITTLE_ENDIAN, \
+ N_("Produce big endian code.") }, \
+ { "no-toc", 0, N_("no description yet") }, \
+ { "toc", MASK_MINIMAL_TOC, N_("no description yet") }, \
+ { "full-toc", MASK_MINIMAL_TOC, N_("no description yet") }, \
+ { "prototype", MASK_PROTOTYPE, N_("no description yet") }, \
+ { "no-prototype", -MASK_PROTOTYPE, N_("no description yet") }, \
+ { "no-traceback", 0, N_("no description yet") }, \
+ { "eabi", MASK_EABI, N_("Use EABI.") }, \
+ { "no-eabi", -MASK_EABI, N_("Don't use EABI.") }, \
+ { "regnames", MASK_REGNAMES, \
+ N_("Use alternate register names.") }, \
+ { "no-regnames", -MASK_REGNAMES, \
+ N_("Don't use alternate register names.") }, \
+ { "sdata", 0, N_("no description yet") }, \
+ { "no-sdata", 0, N_("no description yet") }, \
+ { "sim", 0, \
+ N_("Link with libsim.a, libc.a and sim-crt0.o.") }, \
+ { "ads", 0, \
+ N_("Link with libads.a, libc.a and crt0.o.") }, \
+ { "yellowknife", 0, \
+ N_("Link with libyk.a, libc.a and crt0.o.") }, \
+ { "mvme", 0, \
+ N_("Link with libmvme.a, libc.a and crt0.o.") }, \
+ { "emb", 0, \
+ N_("Set the PPC_EMB bit in the ELF flags header") }, \
+ { "vxworks", 0, N_("no description yet") }, \
+ { "solaris-cclib", 0, N_("no description yet") }, \
+ { "shlib", 0, N_("no description yet") }, \
+ EXTRA_SUBTARGET_SWITCHES \
+ { "newlib", 0, N_("no description yet") },
/* This is meant to be redefined in the host dependent files. */
#define EXTRA_SUBTARGET_SWITCHES
Index: config/sparc/linux.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/linux.h,v
retrieving revision 1.16
diff -u -p -r1.16 linux.h
--- linux.h 2000/06/09 14:31:54 1.16
+++ linux.h 2000/06/26 03:42:29
@@ -1,5 +1,5 @@
/* Definitions for SPARC running Linux-based GNU systems with ELF.
- Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by Eddie C. Dost (ecd@skynet.be)
This file is part of GNU CC.
@@ -89,8 +89,8 @@ Boston, MA 02111-1307, USA. */
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
-{"long-double-64", -MASK_LONG_DOUBLE_128, "Use 64 bit long doubles" }, \
-{"long-double-128", MASK_LONG_DOUBLE_128, "Use 128 bit long doubles" },
+{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
+{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
Index: config/sparc/linux64.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/linux64.h,v
retrieving revision 1.27
diff -u -p -r1.27 linux64.h
--- linux64.h 2000/06/09 14:31:54 1.27
+++ linux64.h 2000/06/26 03:42:29
@@ -1,5 +1,5 @@
/* Definitions for 64-bit SPARC running Linux-based GNU systems with ELF.
- Copyright 1996, 1997, 1998 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
Contributed by David S. Miller (davem@caip.rutgers.edu)
This file is part of GNU CC.
@@ -144,9 +144,9 @@ Boston, MA 02111-1307, USA. */
#define SPARC_DEFAULT_CMODEL CM_MEDLOW
#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"long-double-64", -MASK_LONG_DOUBLE_128, "Use 64 bit long doubles" }, \
-{"long-double-128", MASK_LONG_DOUBLE_128, "Use 128 bit long doubles" },
+#define SUBTARGET_SWITCHES \
+{"long-double-64", -MASK_LONG_DOUBLE_128, N_("Use 64 bit long doubles") }, \
+{"long-double-128", MASK_LONG_DOUBLE_128, N_("Use 128 bit long doubles") },
#undef WCHAR_TYPE
#define WCHAR_TYPE "int"
Index: config/sparc/sp64-elf.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sp64-elf.h,v
retrieving revision 1.11
diff -u -p -r1.11 sp64-elf.h
--- sp64-elf.h 2000/03/06 18:51:52 1.11
+++ sp64-elf.h 2000/06/26 03:42:30
@@ -81,8 +81,8 @@ crtbegin.o%s \
/* V9 chips can handle either endianness. */
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN, "Generate code for big endian" }, \
-{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" },
+{"big-endian", -MASK_LITTLE_ENDIAN, N_("Generate code for big endian") }, \
+{"little-endian", MASK_LITTLE_ENDIAN, N_("Generate code for little endian") },
#undef BYTES_BIG_ENDIAN
#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
Index: config/sparc/sparc.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.h,v
retrieving revision 1.114
diff -u -p -r1.114 sparc.h
--- sparc.h 2000/06/09 14:31:54 1.114
+++ sparc.h 2000/06/26 03:42:34
@@ -1,6 +1,6 @@
/* Definitions of target machine for GNU compiler, for Sun SPARC.
Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
- Free Software Foundation, Inc.
+ 2000 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com).
64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
at Cygnus Support.
@@ -574,46 +574,82 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"fpu", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \
- {"no-fpu", -MASK_FPU, "Do not use hardware fp" }, \
+ { {"fpu", MASK_FPU | MASK_FPU_SET, \
+ N_("Use hardware fp") }, \
+ {"no-fpu", -MASK_FPU, \
+ N_("Do not use hardware fp") }, \
{"no-fpu", MASK_FPU_SET, NULL, }, \
- {"hard-float", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \
- {"soft-float", -MASK_FPU, "Do not use hardware fp" }, \
- {"soft-float", MASK_FPU_SET, NULL }, \
- {"epilogue", MASK_EPILOGUE, "Use FUNCTION_EPILOGUE" }, \
- {"no-epilogue", -MASK_EPILOGUE, "Do not use FUNCTION_EPILOGUE" }, \
- {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, "Assume possible double misalignment" },\
- {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, "Assume all doubles are aligned" }, \
- {"impure-text", MASK_IMPURE_TEXT, "Pass -assert pure-text to linker" }, \
- {"no-impure-text", -MASK_IMPURE_TEXT, "Do not pass -assert pure-text to linker" }, \
- {"flat", MASK_FLAT, "Use flat register window model" }, \
- {"no-flat", -MASK_FLAT, "Do not use flat register window model" }, \
- {"app-regs", MASK_APP_REGS, "Use ABI reserved registers" }, \
- {"no-app-regs", -MASK_APP_REGS, "Do not use ABI reserved registers" }, \
- {"hard-quad-float", MASK_HARD_QUAD, "Use hardware quad fp instructions" }, \
- {"soft-quad-float", -MASK_HARD_QUAD, "Do not use hardware quad fp instructions" }, \
- {"v8plus", MASK_V8PLUS, "Compile for v8plus ABI" }, \
- {"no-v8plus", -MASK_V8PLUS, "Do not compile for v8plus ABI" }, \
- {"vis", MASK_VIS, "Utilize Visual Instruction Set" }, \
- {"no-vis", -MASK_VIS, "Do not utilize Visual Instruction Set" }, \
+ {"hard-float", MASK_FPU | MASK_FPU_SET, \
+ N_("Use hardware fp") }, \
+ {"soft-float", -MASK_FPU, \
+ N_("Do not use hardware fp") }, \
+ {"soft-float", MASK_FPU_SET, NULL }, \
+ {"epilogue", MASK_EPILOGUE, \
+ N_("Use FUNCTION_EPILOGUE") }, \
+ {"no-epilogue", -MASK_EPILOGUE, \
+ N_("Do not use FUNCTION_EPILOGUE") }, \
+ {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
+ N_("Assume possible double misalignment") }, \
+ {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
+ N_("Assume all doubles are aligned") }, \
+ {"impure-text", MASK_IMPURE_TEXT, \
+ N_("Pass -assert pure-text to linker") }, \
+ {"no-impure-text", -MASK_IMPURE_TEXT, \
+ N_("Do not pass -assert pure-text to linker") }, \
+ {"flat", MASK_FLAT, \
+ N_("Use flat register window model") }, \
+ {"no-flat", -MASK_FLAT, \
+ N_("Do not use flat register window model") }, \
+ {"app-regs", MASK_APP_REGS, \
+ N_("Use ABI reserved registers") }, \
+ {"no-app-regs", -MASK_APP_REGS, \
+ N_("Do not use ABI reserved registers") }, \
+ {"hard-quad-float", MASK_HARD_QUAD, \
+ N_("Use hardware quad fp instructions") }, \
+ {"soft-quad-float", -MASK_HARD_QUAD, \
+ N_("Do not use hardware quad fp instructions") }, \
+ {"v8plus", MASK_V8PLUS, \
+ N_("Compile for v8plus ABI") }, \
+ {"no-v8plus", -MASK_V8PLUS, \
+ N_("Do not compile for v8plus ABI") }, \
+ {"vis", MASK_VIS, \
+ N_("Utilize Visual Instruction Set") }, \
+ {"no-vis", -MASK_VIS, \
+ N_("Do not utilize Visual Instruction Set") }, \
/* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
- {"cypress", 0, "Optimize for Cypress processors" }, \
- {"sparclite", 0, "Optimize for SparcLite processors" }, \
- {"f930", 0, "Optimize for F930 processors" }, \
- {"f934", 0, "Optimize for F934 processors" }, \
- {"v8", 0, "Use V8 Sparc ISA" }, \
- {"supersparc", 0, "Optimize for SuperSparc processors" }, \
- /* End of deprecated options. */ \
- {"ptr64", MASK_PTR64, "Pointers are 64-bit" }, \
- {"ptr32", -MASK_PTR64, "Pointers are 32-bit" }, \
- {"32", -MASK_64BIT, "Use 32-bit ABI" }, \
- {"64", MASK_64BIT, "Use 64-bit ABI" }, \
- {"stack-bias", MASK_STACK_BIAS, "Use stack bias" }, \
- {"no-stack-bias", -MASK_STACK_BIAS, "Do not use stack bias" }, \
- {"faster-structs", MASK_FASTER_STRUCTS, "Use structs on stronger alignment for double-word copies" }, \
- {"no-faster-structs", -MASK_FASTER_STRUCTS, "Do not use structs on stronger alignment for double-word copies" }, \
- {"relax", 0, "Optimize tail call instructions in assembler and linker" }, \
- {"no-relax", 0, "Do not optimize tail call instructions in assembler or linker" }, \
+ {"cypress", 0, \
+ N_("Optimize for Cypress processors") }, \
+ {"sparclite", 0, \
+ N_("Optimize for SparcLite processors") }, \
+ {"f930", 0, \
+ N_("Optimize for F930 processors") }, \
+ {"f934", 0, \
+ N_("Optimize for F934 processors") }, \
+ {"v8", 0, \
+ N_("Use V8 Sparc ISA") }, \
+ {"supersparc", 0, \
+ N_("Optimize for SuperSparc processors") }, \
+ /* End of deprecated options. */ \
+ {"ptr64", MASK_PTR64, \
+ N_("Pointers are 64-bit") }, \
+ {"ptr32", -MASK_PTR64, \
+ N_("Pointers are 32-bit") }, \
+ {"32", -MASK_64BIT, \
+ N_("Use 32-bit ABI") }, \
+ {"64", MASK_64BIT, \
+ N_("Use 64-bit ABI") }, \
+ {"stack-bias", MASK_STACK_BIAS, \
+ N_("Use stack bias") }, \
+ {"no-stack-bias", -MASK_STACK_BIAS, \
+ N_("Do not use stack bias") }, \
+ {"faster-structs", MASK_FASTER_STRUCTS, \
+ N_("Use structs on stronger alignment for double-word copies") }, \
+ {"no-faster-structs", -MASK_FASTER_STRUCTS, \
+ N_("Do not use structs on stronger alignment for double-word copies") }, \
+ {"relax", 0, \
+ N_("Optimize tail call instructions in assembler and linker") }, \
+ {"no-relax", 0, \
+ N_("Do not optimize tail call instructions in assembler or linker") }, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT, ""}}
@@ -668,11 +704,14 @@ extern enum processor_type sparc_cpu;
#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
#define TARGET_OPTIONS \
-{ \
- { "cpu=", &sparc_select[1].string, "Use features of and schedule code for given CPU" }, \
- { "tune=", &sparc_select[2].string, "Schedule code for given CPU" }, \
- { "cmodel=", &sparc_cmodel_string, "Use given Sparc code model" }, \
- SUBTARGET_OPTIONS \
+{ \
+ { "cpu=", &sparc_select[1].string, \
+ N_("Use features of and schedule code for given CPU") }, \
+ { "tune=", &sparc_select[2].string, \
+ N_("Schedule code for given CPU") }, \
+ { "cmodel=", &sparc_cmodel_string, \
+ N_("Use given Sparc code model") }, \
+ SUBTARGET_OPTIONS \
}
/* This is meant to be redefined in target specific files. */
Index: config/sparc/splet.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/splet.h,v
retrieving revision 1.7
diff -u -p -r1.7 splet.h
--- splet.h 2000/03/13 17:34:56 1.7
+++ splet.h 2000/06/26 03:42:35
@@ -1,5 +1,5 @@
/* Definitions of target machine for GNU compiler, for SPARClet.
- Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This file is part of GNU CC.
@@ -25,9 +25,9 @@ Boston, MA 02111-1307, USA. */
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#undef SUBTARGET_SWITCHES
-#define SUBTARGET_SWITCHES \
-{"big-endian", -MASK_LITTLE_ENDIAN, "Generate code for big endian" }, \
-{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" },
+#define SUBTARGET_SWITCHES \
+{"big-endian", -MASK_LITTLE_ENDIAN, N_("Generate code for big endian") }, \
+{"little-endian", MASK_LITTLE_ENDIAN, N_("Generate code for little endian") },
#undef ASM_SPEC
#define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)"
Index: config/v850/v850.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/v850/v850.h,v
retrieving revision 1.27
diff -u -p -r1.27 v850.h
--- v850.h 2000/03/29 13:10:44 1.27
+++ v850.h 2000/06/26 03:42:37
@@ -1,5 +1,5 @@
/* Definitions of target machine for GNU compiler. NEC V850 series
- Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
This file is part of GNU CC.
@@ -115,25 +115,25 @@ extern int target_flags;
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- {{ "ghs", MASK_GHS, "Support Green Hills ABI" }, \
+ {{ "ghs", MASK_GHS, N_("Support Green Hills ABI") }, \
{ "no-ghs", -MASK_GHS, "" }, \
{ "long-calls", MASK_LONG_CALLS, \
- "Prohibit PC relative function calls" },\
+ N_("Prohibit PC relative function calls") },\
{ "no-long-calls", -MASK_LONG_CALLS, "" }, \
{ "ep", MASK_EP, \
- "Reuse r30 on a per function basis" }, \
+ N_("Reuse r30 on a per function basis") }, \
{ "no-ep", -MASK_EP, "" }, \
{ "prolog-function", MASK_PROLOG_FUNCTION, \
- "Use stubs for function prologues" }, \
+ N_("Use stubs for function prologues") }, \
{ "no-prolog-function", -MASK_PROLOG_FUNCTION, "" }, \
{ "space", MASK_EP | MASK_PROLOG_FUNCTION, \
- "Same as: -mep -mprolog-function" }, \
- { "debug", MASK_DEBUG, "Enable backend debugging" }, \
+ N_("Same as: -mep -mprolog-function") }, \
+ { "debug", MASK_DEBUG, N_("Enable backend debugging") }, \
{ "v850", MASK_V850, \
- "Compile for the v850 processor" }, \
+ N_("Compile for the v850 processor") }, \
{ "v850", -(MASK_V850 ^ MASK_CPU), "" }, \
{ "big-switch", MASK_BIG_SWITCH, \
- "Use 4 byte entries in switch tables" },\
+ N_("Use 4 byte entries in switch tables") },\
{ "", MASK_DEFAULT, ""}}
/* Information about the various small memory areas. */
@@ -177,13 +177,13 @@ extern struct small_memory_info small_me
#define TARGET_OPTIONS \
{ \
{ "tda=", &small_memory[ (int)SMALL_MEMORY_TDA ].value, \
- "Set the max size of data eligible for the TDA area" }, \
+ N_("Set the max size of data eligible for the TDA area") }, \
{ "tda-", &small_memory[ (int)SMALL_MEMORY_TDA ].value, "" }, \
{ "sda=", &small_memory[ (int)SMALL_MEMORY_SDA ].value, \
- "Set the max size of data eligible for the SDA area" }, \
+ N_("Set the max size of data eligible for the SDA area") }, \
{ "sda-", &small_memory[ (int)SMALL_MEMORY_SDA ].value, "" }, \
{ "zda=", &small_memory[ (int)SMALL_MEMORY_ZDA ].value, \
- "Set the max size of data eligible for the ZDA area" }, \
+ N_("Set the max size of data eligible for the ZDA area") }, \
{ "zda-", &small_memory[ (int)SMALL_MEMORY_ZDA ].value, "" }, \
}
--
Philipp Thomas <pthomas@suse.de>
Development, SuSE GmbH, Schanzaecker Str. 10, D-90443 Nuremberg, Germany
#define NINODE 50 /* number of in core inodes */
#define NPROC 30 /* max number of processes */
-- Version 7 UNIX for PDP 11, /usr/include/sys/param.h