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rs6000 minor cleanups
- To: gcc-patches at gcc dot gnu dot org
- Subject: rs6000 minor cleanups
- From: David Edelsohn <dje at watson dot ibm dot com>
- Date: Thu, 25 May 2000 14:30:00 -0400
The following patch which has been committed better optimizes use
of 64-bit PowerPC instructions when "string" instructions are used for
block moves.
It also decorates a few more casts with "unsigned", cleans up the
use of arguments in the RETURN_ADDR_RTX macros, and gives more patterns
internal names to clarify RTL dumps.
David
* rs6000.c (expand_block_move): Add 64-bit PowerPC doubleword move
to STRING case. Use doubleword STRING move for TARGET_POWERPC64
when unaligned.
* rs6000.h (CONST_OK_FOR_LETTER_P, 'J'): unsigned HOST_WIDE_INT.
(RETURN_ADDR_RTX): Use COUNT and FRAME, not count and frame.
(LEGITIMIZE_RELOAD_ADDRESS): unsigned HOST_WIDE_INT high.
* rs6000.md: Name various internal patterns.
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.124
diff -c -p -r1.124 rs6000.c
*** rs6000.c 2000/05/16 22:59:41 1.124
--- rs6000.c 2000/05/25 18:13:56
*************** expand_block_move (operands)
*** 2369,2375 ****
GEN_INT (move_bytes),
align_rtx));
}
! else if (bytes > 4 && ! TARGET_POWERPC64)
{ /* move up to 8 bytes at a time */
move_bytes = (bytes > 8) ? 8 : bytes;
emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
--- 2369,2388 ----
GEN_INT (move_bytes),
align_rtx));
}
! else if (bytes >= 8 && TARGET_POWERPC64
! /* 64-bit loads and stores require word-aligned displacements. */
! && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
! {
! move_bytes = 8;
! tmp_reg = gen_reg_rtx (DImode);
! emit_move_insn (tmp_reg,
! expand_block_move_mem (DImode,
! src_addr, orig_src));
! emit_move_insn (expand_block_move_mem (DImode,
! dest_addr, orig_dest),
! tmp_reg);
! }
! else if (bytes > 4)
{ /* move up to 8 bytes at a time */
move_bytes = (bytes > 8) ? 8 : bytes;
emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode,
*************** addrs_ok_for_quad_peep (addr1, addr2)
*** 3000,3006 ****
offset1 = 0;
}
! /* Make sure the second address is a (mem (plus (reg) (const_int). */
if (GET_CODE (addr2) != PLUS)
return 0;
--- 3013,3019 ----
offset1 = 0;
}
! /* Make sure the second address is a (mem (plus (reg) (const_int))). */
if (GET_CODE (addr2) != PLUS)
return 0;
Index: rs6000.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.80
diff -c -p -r1.80 rs6000.h
*** rs6000.h 2000/05/14 21:43:44 1.80
--- rs6000.h 2000/05/25 18:13:57
*************** enum reg_class
*** 1056,1062 ****
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
! : (C) == 'J' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff0000u)) == 0 \
: (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
: (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
&& ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
--- 1056,1062 ----
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
! : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) == 0 \
: (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
: (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
&& ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
*************** typedef struct rs6000_args
*** 1622,1629 ****
/* The current return address is in link register (65). The return address
of anything farther back is accessed normally at an offset of 8 from the
frame pointer. */
! #define RETURN_ADDR_RTX(count, frame) \
! ((count == -1) \
? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) \
: gen_rtx_MEM (Pmode, \
memory_address \
--- 1622,1629 ----
/* The current return address is in link register (65). The return address
of anything farther back is accessed normally at an offset of 8 from the
frame pointer. */
! #define RETURN_ADDR_RTX(COUNT, FRAME) \
! (((COUNT) == -1) \
? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) \
: gen_rtx_MEM (Pmode, \
memory_address \
*************** typedef struct rs6000_args
*** 1631,1637 ****
plus_constant (copy_to_reg \
(gen_rtx_MEM (Pmode, \
memory_address (Pmode, \
! frame))), \
RETURN_ADDRESS_OFFSET))))
/* Definitions for register eliminations.
--- 1631,1637 ----
plus_constant (copy_to_reg \
(gen_rtx_MEM (Pmode, \
memory_address (Pmode, \
! (FRAME)))), \
RETURN_ADDRESS_OFFSET))))
/* Definitions for register eliminations.
*************** do {
*** 1935,1942 ****
{ \
HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
! HOST_WIDE_INT high \
! = (((val - low) & 0xffffffffu) ^ 0x80000000u) - 0x80000000u; \
\
/* Check for 32-bit overflow. */ \
if (high + low != val) \
--- 1935,1942 ----
{ \
HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
! unsigned HOST_WIDE_INT high \
! = (((val - low) & 0xffffffffu) ^ 0x80000000u) - 0x80000000u; \
\
/* Check for 32-bit overflow. */ \
if (high + low != val) \
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.87
diff -c -p -r1.87 rs6000.md
*** rs6000.md 2000/05/14 21:42:32 1.87
--- rs6000.md 2000/05/25 18:13:58
***************
*** 7552,7558 ****
}
}")
! (define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
"gpc_reg_operand (operands[0], SImode)
--- 7552,7558 ----
}
}")
! (define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
(match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
"gpc_reg_operand (operands[0], SImode)
***************
*** 7592,7598 ****
operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
}")
! (define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
(const_int 0)))
--- 7592,7598 ----
operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
}")
! (define_insn "*movsi_internal2"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
(const_int 0)))
***************
*** 8182,8188 ****
}
}")
! (define_insn "*movdi_32"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
(match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
"! TARGET_POWERPC64
--- 8182,8188 ----
}
}")
! (define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
(match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
"! TARGET_POWERPC64
***************
*** 8264,8270 ****
operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
}")
! (define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
(match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
"TARGET_POWERPC64
--- 8264,8270 ----
operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
}")
! (define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
(match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
"TARGET_POWERPC64
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 8494,8500 ****
#endif
}")
! (define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
(const_int 0)))
--- 8494,8500 ----
#endif
}")
! (define_insn "*movdi_internal2"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
(const_int 0)))
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 8505,8511 ****
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
!
(define_split
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
--- 8505,8511 ----
#"
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
!
(define_split
[(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 8517,8523 ****
(compare:CC (match_dup 0)
(const_int 0)))]
"")
!
;; TImode is similar, except that we usually want to compute the address into
;; a register and use lsi/stsi (the exception is during reload). MQ is also
;; clobbered in stsi for POWER, so we need a SCRATCH for it.
--- 8517,8523 ----
(compare:CC (match_dup 0)
(const_int 0)))]
"")
!
;; TImode is similar, except that we usually want to compute the address into
;; a register and use lsi/stsi (the exception is during reload). MQ is also
;; clobbered in stsi for POWER, so we need a SCRATCH for it.
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10682,10688 ****
}")
;; Here are the actual compare insns.
! (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
--- 10682,10688 ----
}")
;; Here are the actual compare insns.
! (define_insn "*cmpsi_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10690,10696 ****
"{cmp%I2|cmpw%I2} %0,%1,%2"
[(set_attr "type" "compare")])
! (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
--- 10690,10696 ----
"{cmp%I2|cmpw%I2} %0,%1,%2"
[(set_attr "type" "compare")])
! (define_insn "*cmpdi_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10726,10732 ****
operands[5] = GEN_INT (sextc);
}")
! (define_insn ""
[(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
--- 10726,10732 ----
operands[5] = GEN_INT (sextc);
}")
! (define_insn "*cmpsi_internal2"
[(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10734,10740 ****
"{cmpl%I2|cmplw%I2} %0,%1,%W2"
[(set_attr "type" "compare")])
! (define_insn ""
[(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
(compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
--- 10734,10740 ----
"{cmpl%I2|cmplw%I2} %0,%1,%W2"
[(set_attr "type" "compare")])
! (define_insn "*cmpdi_internal2"
[(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
(compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10787,10793 ****
[(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
! (define_insn ""
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
--- 10787,10793 ----
[(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
! (define_insn "*cmpsf_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
*************** operands[2] = GEN_INT (INTVAL (operands[
*** 10795,10801 ****
"fcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")])
! (define_insn ""
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]
--- 10795,10801 ----
"fcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")])
! (define_insn "*cmpdf_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))]