Re: fuse multiple ops into one new op

[Cherry Vanc <cherry dot vanc at gmail dot com>]

I forgot to mention that this define_insn pattern doesnt work for me.

On Tue, Aug 5, 2014 at 4:26 PM, Cherry Vanc <cherry.vanc@gmail.com> wrote:
> Thanks. I am now using a define_insn based on your inputs :
>
> (define_insn "testnew36"
>   [(set (match_operand:DI 0 "register_operand" "")
>     (op1:DI (match_operand:DI 1 "register_operand" "")
> (match_operand:SI 2 "immediate_operand" "") ))
>   (set (match_operand:DI 3 "register_operand" "")
>     (op2:DI (match_operand:DI 4 "register_operand" "") (match_dup 0)))
>   (set (match_operand:DI 5 "register_operand" "")
>     (sign_extend:DI (op3:SI (match_dup 3))))]
>   "TARGET_MYCORE"
>   "testnew 36"
>   [(set_attr "mode" "DI")])
>
> Why doesnt -fdump-rtl-all-all / -fdump-rtl-all generate those .life
> and .combine files so that I can take a look at the combine pass is
> doing ? dump-rtl-combine doesnt spit anything either. MYCORE is a mips
> adaptation using GCC 4.9.0.
>
>
> On Sat, Aug 2, 2014 at 2:51 AM, Jeff Law <law@redhat.com> wrote:
>> On 08/01/14 17:18, Cherry Vanc wrote:
>>>
>>> I need to fuse multiple instructions into a single one.
>>> ...
>>> r1 = (r1) op1 (const)
>>> ...
>>> ...
>>> r1 = (r1) op2 (r2)
>>> ...
>>> ...
>>> r3 = op3 (r1)
>>> ...
>>>
>>> I defined a peephole2 pattern in my GCC backend .md file. If these
>>> three instructions are contiguous, then I do get my test "testnew"
>>> instruction. If these instructions are far apart, I dont.
>>>
>>> (define_peephole2
>>>    [(set (match_operand:DI 0 "register_operand" "")
>>>      (op1:DI (match_dup 0) (match_operand:SI 1 "immediate_operand" "") ))
>>>    (set (match_dup 0)
>>>      (op2:DI (match_operand:DI 2 "register_operand" "") (match_dup 0)))
>>>    (set (match_dup 0)
>>>      (sign_extend:DI (op3:SI (match_dup 0))))]
>>>    "TARGET_MYCORE"
>>>    [(set (match_dup 0) (sign_extend:DI (op3:SI (op2:SI (op1:SI
>>> (match_dup 0) (match_dup 1)) (match_dup 0)))))]
>>>    "")
>>>
>>> (define_insn "*testnew"
>>>    [(set (match_operand:DI 0 "register_operand" "=d")
>>>          (sign_extend:DI (op3:SI (op2:SI (op1:SI (match_dup 0)
>>> (match_operand:SI 1 "immediate_operand" "I")) (match_dup 0)))))]
>>>    "TARGET_MYCORE"
>>>    "testnew 36"
>>>    [(set_attr "mode" "DI")])
>>>
>>> How can I fuse multiple instructions that are far apart into a new
>>> single opcode that MYCORE has ?
>>
>> I suspect the problem is "r1" is set/used multiple times.  That will inhibit
>> instruction combination.  If at all possible you really want that code to
>> look like:
>>
>>
>> r4 = (r1) op1 (const)  /* r1 dies */
>> r5 = r4 op (r2) /*r2 and r2 die */
>> r3 = op3 (r5) /* r5 dies */
>>
>>
>> Then the combiner will attempt to combine those instructions in the obvious
>> ways.  For the combiner you want to use a define_insn pattern.
>>
>> define_peephole2 is primarily used in cases where there is no obvious
>> dataflow between the patterns.
>>
>>
>> Jeff
>>
>>