Re: builtin assembler constraints

[Chung-Ju Wu <jasonwucj at gmail dot com>]

2013/2/10 Ian Lance Taylor <iant@google.com>:
> On Sat, Feb 9, 2013 at 7:37 AM, Georg-Johann Lay <gjl@gcc.gnu.org> wrote:
>> Ian Lance Taylor schrieb:
>>
>>> As far as I know there is no constraint that describes only the even
>>> registers of the general register set.  It would not be very difficult
>>> to add one to the PPC backend.  I can't think of any other way to
>>> approach this.
>>
>>
>> AFAIK that does not work because the respective register class would have
>> holes.  You cannot have a register class that contains only even registers
>> and omits the odd ones.  Or can IRA / reload handle this now?
>
> To the best of my knowledge it always could.  Register classes
> routinely have holes.  I'm not sure what sort of problem you are
> thinking of.
>

I guess Georg refers to this situation:

EVEN_SET_REGISTERS: $r0, $r2, $r4, $r6, ...
ODD_SET_REGISTERS: $r1, $r3, $r5, $r7, ...

And IRA/reload cannot allocate $r0+$r2 for DImode/DFmode.
Because a reg rtx with a machine mode that specifies more than
one word actually represents several consecutive hardware registers.


But if we design register class in this way:
(I think this is what you meant "routinely have holes"~ ^^)

LOW_SET_REGISTERS: $r0, $r1, $r2, $r3, $r8, $r9, $r10, $r11
HIGH_SET_REGISTERS: $r4, $r5, $r6, $r7, $r12, $r13, $r14, $r15

plus we design HARD_REGNO_NREGS and HARD_REGNO_MODE_OK
with ABI properly. Then that is fine.
IRA/reload are able to allocate $r0+$r1 for DImode/DFmode.


Best regards,
jasonwucj