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Re: Bit field ordering on Big-Endian (SPARC) processor
- From: PaweÅ Sikora <pluto at agmk dot net>
- To: gcc-help at gcc dot gnu dot org, its dot dipanjan dot das at gmail dot com
- Cc: Gert Hulselmans <hulselmansgert at gmail dot com>
- Date: Tue, 11 Dec 2012 18:04:40 +0100
- Subject: Re: Bit field ordering on Big-Endian (SPARC) processor
- References: <CAEK-7JKpdPA2C+3kkWc5yVbG2Gy=ahuq+bThKuN4XDu9cS4GdA@mail.gmail.com>
On Tuesday 11 of December 2012 18:31:06 Dipanjan Das wrote:
> Consider the code below:
>
> #define FORCE_CAST(var, type) *(type*)&var
^^^^^^^^^^^^^^^^ don't forget to use -fno-strict-aliasing with such ugly tricks.
> struct processor_status_register
> {
> unsigned int cwp:5;
> unsigned int et:1;
> unsigned int ps:1;
> unsigned int s:1;
> unsigned int pil:4;
> unsigned int ef:1;
> unsigned int ec:1;
> unsigned int reserved:6;
>
> unsigned int c:1;
> unsigned int v:1;
> unsigned int z:1;
> unsigned int n:1;
>
> unsigned int ver:4;
> unsigned int impl:4;
> }__attribute__ ((__packed__));
iirc, the C language gives no guarantee of the ordering of fields within machine words,
so if you use them for the h/w register modeling, you program will not only be nonportable,
it will be compiler-dependent too. you should really read suitable byte/word/doubleword
from mapped h/w memory, convert it with le/be_to_cpu() method and shift/mask to access bits.
BR,
PaweÅ.